Online edition: ISSN 2432-6380
[TOP] | [2017] | [2018] | [2019] | [2020] | [2021] | [2022] | [2023] | [Japanese] / [English]
DC2020-80
The necessity of exploiting various types of memory devices
-- Discussion based on behavior analysis of molecular dynamics simulation, GROMACS --
Hiroyoshi Kodama, Hiroshi Endo, Takahide Yoshikawa (F-lab)
pp. 1 - 6
DC2020-81
A Compaction Offloading Method for LSM-Tree in Storage Disaggregation Architecture
Shun Gokita, Jun Kato, Masataka Sonoda, Osamu Shiraki, Makoto Hamaminato (Fujitsu Lab)
pp. 7 - 12
DC2020-82
A Remote Driving System by Using RC Car
Shotaro Takahashi, Hayato Nomura (NITAC)
pp. 13 - 18
DC2020-83
(See Japanese page.)
pp. 19 - 24
DC2020-84
Scheduling algorithms for sporadic and periodic tasks in multiprocessors
Yuki Mori, Nobuyuki Yamasaki (Keio Univ.)
pp. 25 - 30
DC2020-85
Parallelization and Vectorization of SpMM for Sparse Neural Network
Yuta Tadokoro, Keiji Kimura, Hironori Kasahara (Waseda Univ.)
pp. 31 - 36
DC2020-86
Optimizing Data Transfer between CPU and GPU in Model Parallel Training with Mesh TensorFlow
Hironori Yokote, Shinobu Miwa, Hayato Yamaki, Hiroki Honda (UEC)
pp. 37 - 42
DC2020-87
Optimal placement of coherence directories using memory networks
Yuki Kameyama, Yoshiya Shikama, Naoya Niwa (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.)
pp. 43 - 48
DC2020-88
Prototyping of A Packet Aggregation/Disaggregation Router with FPGA
Shiro Takayama, Naoki Fujieda, Michihiro Aoki (Aichi Inst. of Tech.)
pp. 49 - 54
DC2020-89
Performance Evaluation of High-bandwidth Low-latency Approximate Networks with Performance Fluctuation
Shoichi Hirasawa, Michihiro Koibuchi (NII)
pp. 55 - 60
DC2020-90
Unsupervised Recycled FPGA Detection Using Direct Density Ratio Estimation Based on Self-referencing
Yuya Isaka (KGU), Michihiro Shintani (NAIST), Foisal Ahmed (PU), Michiko Inoue (NAIST)
pp. 61 - 66
DC2020-91
An Estimation Method of a Defect Types for Suspected Fault Lines in Logical Faulty VLSI Using Neural Networks
Natsuki Ota, Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.), Yukari Yamauchi, Masayuki Arai (Nihon Univ.)
pp. 67 - 72
DC2020-92
A Don't Care Filling Method of Control Signals for Controllers to Enhance Fault Diagnosability at Register Transfer Level
Kohei Tsuchibuchi, Toshinori Hosokawa (Nihon Univ), Koji Yamazaki (Meiji Univ.)
pp. 73 - 78
DC2020-93
A Controller Augmentation method to Improving Transition Fault Coverage
Kyohei Iizuka, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ)
pp. 79 - 84
DC2020-94
A Logic Locking Method Based on Anti-SAT at Register Transfer Level
Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.)
pp. 85 - 90
DC2020-95
IPC control mechanism for highly efficient RT-DVFS
Atsushi Santo, Nobuyuki Yamasaki (Keio Univ.)
pp. 91 - 96
DC2020-96
Non Stop Processor with Non Volatile Element
Shota Nakabeppu, Nao Sugiyama, Nobuyuki Yamasaki (Keio Univ.), Kenta Suzuki, Keizo Hiraga, Yasuo Kanda (Sony Semiconductor Solutions)
pp. 97 - 102
DC2020-97
A Neural ODE Based Domain Adaptation Method for Edge Devices
Hiroki Kawakami, Hirohisa Watanabe, Hiroki Matsutani (Keio Univ.)
pp. 103 - 108
DC2020-98
A Light-Weight Fine-Tuning Method using OS-ELM for FPGAs
Takeya Yamada, Mineto Tsukada, Hiroki Matsutani (Keio univ.)
pp. 109 - 114
DC2020-99
Implementation of Versatile Tensor Accelarator (VTA) on the Flow-in-Cloud FPGA system
Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano (Keio Univ.)
pp. 115 - 120
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.