IEICE Technical Report

Online edition: ISSN 2432-6380

Volume 125, Number 342

Reconfigurable Systems

Workshop Date : 2026-01-27 - 2026-01-28 / Issue Date : 2026-01-20

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Table of contents

RECONF2025-118
QARDE: A CV-QKD-based Adaptive Reconfigurable NB-LDPC Decoder Engine for RFSoC FPGA Systems
Kaijie Wei (Keio Univ.), Devanshu Garg (blueqat Inc.), Ryutaro Nagai (SCSK Corp.), Takao Tomono (Keio Univ.), Hideharu Amano (UTokyo)
pp. 1 - 6

RECONF2025-119
RDMA and PR mechanism for Middle Scale FPGA clusters
Keisuke Takano (JAIST)
pp. 7 - 11

RECONF2025-120
Design and Implementation of a Verilog HDL Compiler to Accelerate RTL Simulation
Lennart Trunk, Yuki Yagi, Kenji Kise (Science Tokyo)
pp. 12 - 17

RECONF2025-121
A study of Implementing UWB Vehicle-to-Vehicle Ranging Platform on ZYNQ
Deng Weicheng, Kanazawa Kenji (UTsukuba)
pp. 18 - 22

RECONF2025-122
[Invited Talk] Kioxia AiSAQ -- SSD-Based Large-Scale Information Retrieval for Generative AI --
Kento Tatsuno (KIOXIA)
pp. 23 - 27

RECONF2025-123
A study of implementing YOLOv8nano with DPU
Xue jiahui, Kanazawa Kenji (UTsukuba)
pp. 28 - 32

RECONF2025-124
FPGA-Based Design of Multi-Precision Floating-Point Arithmetic Units for Image Recognition Applications
Hiroki Kurihara, Fumiya Kono (SIST)
pp. 33 - 38

RECONF2025-125
(See Japanese page.)
pp. 39 - 44

RECONF2025-126
A large-scale hackathon using AWS F2 instances
Hideharu Amano, Atsutake Kosuge, Yusuke Iwasawa, Hideaki Masuda, Takao Goto, Mizuho Nitami, Makoto Ikeda (Univ. of Tokyo)
pp. 45 - 50

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan