IEICE Technical Report

Online edition: ISSN 2432-6380

Hardware Security

Workshop Date : 2026-04-17 / Issue Date : 2026-04-10

HWS2026-1
Analysis and Evaluation of Side-Channel Attack by Backside of Si-substrate Voltage of Crypt IC Chip
Rikuu Hasegawa (Kobe Univ.), Kazuki Monta, Takuya Wadatsumi (Secafy), Makoto Nagata (Kobe Univ.)
pp. 1 - 5

HWS2026-2
Security of the GPV Framework under Fault Attacks
Tomoka Takahashi, Atsuko Miyaji (Osaka Univ.)
pp. 6 - 11

HWS2026-3
(See Japanese page.)
pp. 12 - 17

HWS2026-4
(See Japanese page.)
pp. 18 - 22

HWS2026-5
Optimizing ASIC Implementations for Attribute-Based Encryption: A Comparison with FPGA Optimized Designs
Kensuke Hayashi, Makoto Ikeda (UTokyo)
pp. 23 - 28

HWS2026-6
Investigation of Polynomial Multiplication Architectures Considering Public Key Size in TFHE
Tomofumi Nakagawa, Ryosuke Matsuo, Makoto Ikeda (The Univ. of Tokyo)
pp. 29 - 34

HWS2026-7
A Note on the Side-Channel Attack Resistance of the Higher-Order Masked ML-DSA
Junichi Sakamoto (AIST)
pp. 35 - 40

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan