| Paper Abstract and Keywords |
| Presentation |
2007-01-18 13:25
Analysis of design architecture of ePLX ( embedded Programmable Logic matriX) and Evaluation of circuit mapping
Tomoo Hishida, Kouta Ishibashi, Shun Kimura, Naoki Okuno, Mitsutaka Matsumoto (Ritsumeikan Univ.), Hirofumi Nakano, Takenobu Iwao, Yoshihiro Okuno, Kazutami Arimoto (Renesas Technology), Tomonori Izumi, Takeshi Fujino (Ritsumeikan Univ.) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
Recently, non-recurring engineering costs (NREs), including cost of mask-sets, and engineering design efforts are critical problems in a small-volume SoC(System on a Chip) manufacturing. FPGAs are used for some electrical products, but FPGAs still have lower performance and higher chip-cost than SoC. In this paper, we propose ePLX(embedded Programmable Logic matriX) that is embedded in SoC. Application-specific or customers-specific logic function in SoC can be changed using ePLX. The ePLX architecture is based on the programmable local-clusters, which are composed of two input Look-Up-Table(LUT) matrix and the D-FlipFlops on the matrix side. The hierarchical wiring resources are located between the local-clusters. We demonstrate the ePLX mapping results for sample circuits such as an adder, a multiplier, and a DES encryption circuit, and discuss LUT utilization efficiency. Lastly, we introduce ePLX design flow from HDL code to ePLX configuration data, and experimental results using the mapping tool which is newly-developed for ePLX. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
programmable device / small grain / LUT matrix / / / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 106, no. 458, RECONF2006-71, pp. 37-42, Jan. 2007. |
| Paper # |
RECONF2006-71 |
| Date of Issue |
2007-01-11 (VLD, CPSY, RECONF) |
| ISSN |
Print edition: ISSN 0913-5685 |
| Download PDF |
|
|