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Paper Abstract and Keywords
Presentation 2007-04-12 11:10
[Invited Talk] A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current
Akira Kotabe, Satoru Hanzawa (Hitachi), Naoki Kitai (Hitachi ULSI), Kenichi Osada, Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura (Hitachi), Masahiro Moniwa (Renesas), Takayuki Kawahara (Hitachi) ICD2007-5
Abstract (in Japanese) (See Japanese page) 
(in English) An experimental 512-kB embedded Phase Change Memory (PCM) is developed in a 0.13-μm 1.5-V CMOS technology. Three circuit techniques were developed to apply the previously developed low-power PCM cell to embedded ROM modules. A sense-amplifier-prefetch serial write scheme and a two-step set method achieve 416-kB/s write-throughput at 100-μA cell current. A charge-transfer direct-sense scheme has a 16-bit parallel read access time of 9.9 ns in a memory array drawing 280 μA. A standby voltage control scheme suppresses leakage current in the memory array and enlarges the range of measurable PCM cell resistance from 3 MΩ to 33 MΩ. These circuit techniques realize a low-power embedded PCM.
Keyword (in Japanese) (See Japanese page) 
(in English) Phase change / Embedded memory / Sense-amplifier-prefetch serial write scheme / Two-step set method / Charge-transfer direct-sense scheme / Standby voltage control scheme / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 1, ICD2007-5, pp. 23-28, April 2007.
Paper # ICD2007-5 
Date of Issue 2007-04-05 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee ICD  
Conference Date 2007-04-12 - 2007-04-13 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2007-04-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current 
Sub Title (in English)  
Keyword(1) Phase change  
Keyword(2) Embedded memory  
Keyword(3) Sense-amplifier-prefetch serial write scheme  
Keyword(4) Two-step set method  
Keyword(5) Charge-transfer direct-sense scheme  
Keyword(6) Standby voltage control scheme  
Keyword(7)  
Keyword(8)  
1st Author's Name Akira Kotabe  
1st Author's Affiliation Hitachi, Ltd. (Hitachi)
2nd Author's Name Satoru Hanzawa  
2nd Author's Affiliation Hitachi, Ltd. (Hitachi)
3rd Author's Name Naoki Kitai  
3rd Author's Affiliation Hitachi ULSI Systems Co. (Hitachi ULSI)
4th Author's Name Kenichi Osada  
4th Author's Affiliation Hitachi, Ltd. (Hitachi)
5th Author's Name Yuichi Matsui  
5th Author's Affiliation Hitachi, Ltd. (Hitachi)
6th Author's Name Nozomu Matsuzaki  
6th Author's Affiliation Hitachi, Ltd. (Hitachi)
7th Author's Name Norikatsu Takaura  
7th Author's Affiliation Hitachi, Ltd. (Hitachi)
8th Author's Name Masahiro Moniwa  
8th Author's Affiliation Renesas Technology Copr. (Renesas)
9th Author's Name Takayuki Kawahara  
9th Author's Affiliation Hitachi, Ltd. (Hitachi)
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Speaker Author-1 
Date Time 2007-04-12 11:10:00 
Presentation Time 50 minutes 
Registration for ICD 
Paper # ICD2007-5 
Volume (vol) vol.107 
Number (no) no.1 
Page pp.23-28 
#Pages 6 
Date of Issue 2007-04-05 (ICD) 

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