Paper Abstract and Keywords |
Presentation |
2007-04-13 09:40
[Invited Talk]
A 65 nm Embedded SRAM with Wafer Level Burn-In Mode, Leak-Bit Redundancy and E-trim Fuse for Known Good Die Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono (Renesas Technology), Yuji Oda (Shikino High-Tech), Susumu Imaoka (Renesas Design), Keiichi Usui (Daioh Electric), Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) ICD2007-11 Link to ES Tech. Rep. Archives: ICD2007-11 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
We propose a Wafer Level Burn-In (WLBI) mode, a leak-bit redundancy and a small, highly reliable Cu E-trim fuse repair scheme for an embedded 6T-SRAM to achieve a KGD-SoC. We fabricated a 16M-SRAM with these techniques using 65 nm LSTP technology, and confirmed its efficient operation. The WLBI mode has almost no area penalty and a speed penalty of only 50 psec. The leak-bit redundancy area penalty is less than 2%. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
6T-SRAM / 65nm CMOS Technology / Known Good Die / Embedded SRAM / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 107, no. 1, ICD2007-11, pp. 59-64, April 2007. |
Paper # |
ICD2007-11 |
Date of Issue |
2007-04-05 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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ICD2007-11 Link to ES Tech. Rep. Archives: ICD2007-11 |
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