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| Presentation | 2008-03-05 15:20 Analog Floorplan with Soft-Module Configuration Kentarou Murata, Kazuya Sasaki, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu)  VLD2007-142 ICD2007-165 Link to ES Tech. Rep. Archives: ICD2007-165 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In MOS analog design, the transistor size is increasing as the supply voltage becomes lower, and the layout configuration of the transistor module is diversified. In this paper, we propose a novel analog floorplan technique for dealing with modules with discrete outline candidates. In our floorplan, rectangular local structures are extracted from a given sequence-pair, and the aspect ratio of every module included in the structure is changed at the same time by an equal scaling ratio for minimizing the chip area. In experiments, the results showed the advantage of our floorplan technique. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Floorplan / Soft-Module / Sequence-Pair / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 107, no. 506, VLD2007-142, pp. 31-36, March 2008. | |
| Paper # | VLD2007-142 | |
| Date of Issue | 2008-02-27 (VLD, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2007-142 ICD2007-165 Link to ES Tech. Rep. Archives: ICD2007-165 |
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| Conference Information | |
| Committee | VLD ICD |
| Conference Date | 2008-03-05 - 2008-03-07 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | TiRuRu |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System-on-silicon design techniques and related VLSs |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2008-03-VLD-ICD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Analog Floorplan with Soft-Module Configuration |
| Sub Title (in English) | |
| Keyword(1) | Floorplan |
| Keyword(2) | Soft-Module |
| Keyword(3) | Sequence-Pair |
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| 1st Author's Name | Kentarou Murata |
| 1st Author's Affiliation | University of Kitakyushu (Univ. of Kitakyushu) |
| 2nd Author's Name | Kazuya Sasaki |
| 2nd Author's Affiliation | University of Kitakyushu (Univ. of Kitakyushu) |
| 3rd Author's Name | Qing Dong |
| 3rd Author's Affiliation | University of Kitakyushu (Univ. of Kitakyushu) |
| 4th Author's Name | Jing Li |
| 4th Author's Affiliation | University of Kitakyushu (Univ. of Kitakyushu) |
| 5th Author's Name | Shigetoshi Nakatake |
| 5th Author's Affiliation | University of Kitakyushu (Univ. of Kitakyushu) |
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| Speaker | Author-1 |
| Date Time | 2008-03-05 15:20:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2007-142, ICD2007-165 |
| Volume (vol) | vol.107 |
| Number (no) | no.506(VLD), no.509(ICD) |
| Page | pp.31-36 |
| #Pages | 6 |
| Date of Issue | 2008-02-27 (VLD, ICD) |
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