Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2008-03-06 10:30
Design and Evaluation of the component circuits for the PLL
Yuko Kitaji, Masayoshi Tachibana (Kochi Univ. of Tech.) VLD2007-147 ICD2007-170
Abstract (in Japanese) (See Japanese page) 
(in English) The PLL circuit consists of the phase detector, the loop filter, the voltage-controlled oscillator, and the divider. In this report, we laid out the components of PLL except the loop filter, then measured and evaluated. We laid out 2 VCOs; that is, Current-Starved VCO and Source-Coupled VCO, 2 Phase Detectors; that is, XOR-Phase Detector and Phase Frequency Detector, and the Divider. In addition, Phase Frequency Detector has 2 outputs, so these outputs should be combined into a single output by using Tri-state or Charge-pump outputs. We used HSPICE for simulation.
Keyword (in Japanese) (See Japanese page) 
(in English) Current-Starved VCO / Source-Coupled VCO / XOR-PD / PFD / PLL / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 507, VLD2007-147, pp. 19-24, March 2008.
Paper # VLD2007-147 
Date of Issue 2008-02-28 (VLD, ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2007-147 ICD2007-170

Conference Information
Committee VLD ICD  
Conference Date 2008-03-05 - 2008-03-07 
Place (in Japanese) (See Japanese page) 
Place (in English) TiRuRu 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System-on-silicon design techniques and related VLSs 
Paper Information
Registration To VLD 
Conference Code 2008-03-VLD-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design and Evaluation of the component circuits for the PLL 
Sub Title (in English)  
Keyword(1) Current-Starved VCO  
Keyword(2) Source-Coupled VCO  
Keyword(3) XOR-PD  
Keyword(4) PFD  
Keyword(5) PLL  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Yuko Kitaji  
1st Author's Affiliation Kochi Univercity of Technology (Kochi Univ. of Tech.)
2nd Author's Name Masayoshi Tachibana  
2nd Author's Affiliation Kochi Univercity of Technology (Kochi Univ. of Tech.)
3rd Author's Name  
3rd Author's Affiliation ()
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2008-03-06 10:30:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2007-147, ICD2007-170 
Volume (vol) vol.107 
Number (no) no.507(VLD), no.510(ICD) 
Page pp.19-24 
#Pages 6 
Date of Issue 2008-02-28 (VLD, ICD) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan