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Paper Abstract and Keywords
Presentation 2009-01-14 10:00
A Low-Power Feild-Programmable VLSI Based on Autonomous Fine-Grain Power-Gating
Masanori Hariyama, Shota Ishihara, Michitaka Kameyama (Tohoku Univ.) ICD2008-138 Link to ES Tech. Rep. Archives: ICD2008-138
Abstract (in Japanese) (See Japanese page) 
(in English) This paper presents a field-programmable VLSI(FPVLSI) based on fine-grain power gating with small overheads. The asynchronous architecture inherently has the information about the activity of a cell. This greatly reduces the area and power overheads of power gating control because a sequencer and a power-control-timing storage are not required.
Detecting data arrival in advance prevents delay for wake-up and unnecessary power switching. The proposed architecture is fabricated in the ASPLA 90nm CMOS process with dual threshold voltages. When the utilization is 20\%, the static power is reduced to 34\%.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / Asynchronous Architecture / Power gating / / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 375, ICD2008-138, pp. 51-55, Jan. 2009.
Paper # ICD2008-138 
Date of Issue 2009-01-06 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2008-138 Link to ES Tech. Rep. Archives: ICD2008-138

Conference Information
Committee ICD IPSJ-ARC IPSJ-EMB  
Conference Date 2009-01-13 - 2009-01-14 
Place (in Japanese) (See Japanese page) 
Place (in English) Shoushin Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Embedded System Platform 
Paper Information
Registration To ICD 
Conference Code 2009-01-ICD-ARC-EMB 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Low-Power Feild-Programmable VLSI Based on Autonomous Fine-Grain Power-Gating 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) Asynchronous Architecture  
Keyword(3) Power gating  
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1st Author's Name Masanori Hariyama  
1st Author's Affiliation Tohoku University (Tohoku Univ.)
2nd Author's Name Shota Ishihara  
2nd Author's Affiliation Tohoku University (Tohoku Univ.)
3rd Author's Name Michitaka Kameyama  
3rd Author's Affiliation Tohoku University (Tohoku Univ.)
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Speaker Author-1 
Date Time 2009-01-14 10:00:00 
Presentation Time 30 minutes 
Registration for ICD 
Paper # ICD2008-138 
Volume (vol) vol.108 
Number (no) no.375 
Page pp.51-55 
#Pages
Date of Issue 2009-01-06 (ICD) 


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