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Paper Abstract and Keywords
Presentation 2009-11-20 13:55
Measurement Techniques for On-chip Power Supply Noise Waveforms based on Delay Observation in Inverter Chain Circuits
Yutaka Uematsu, Hideki Osaka, Eiichi Suzuki, Masayoshi Yagyu, Tatsuya Saito (Hitachi Co Ltd.) EMCJ2009-83
Abstract (in Japanese) (See Japanese page) 
(in English) To evaluate an on-chip power supply noise waveforms for power integrity design, we have developed a
technique for measuring on-chip voltage waveforms. To overcome the trade-off in the voltage resolution and the
measurable frequency band, we designed inverter chain circuits that have the different lengths of series inverters: the
short chain provides the high frequency and the low resolution, while the long chain provides the low frequency and the high resolution. We measured the on-chip noise waveforms using a 90-nm CMOS test chip with a 50-inverter chain circuit as small as 320 square micrometers, confirming that the circuit could achieve a voltage resolution of 1 mV and temporal resolution of 20 ps. The amplitude of the noise waveform generated by the noise source circuits is proportional to the activating ratio of the synchronized inverter group, although resonance frequencies are virtually
the same - 160 MHz - when the activating ratios change.
Keyword (in Japanese) (See Japanese page) 
(in English) power integrity design / power supply noise / power integrity / chip-pkg resonance / / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 295, EMCJ2009-83, pp. 25-30, Nov. 2009.
Paper # EMCJ2009-83 
Date of Issue 2009-11-13 (EMCJ) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee EMCJ  
Conference Date 2009-11-20 - 2009-11-20 
Place (in Japanese) (See Japanese page) 
Place (in English) Aoyama Gakuin Univ. (Aoyama Campus) 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To EMCJ 
Conference Code 2009-11-EMCJ 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Measurement Techniques for On-chip Power Supply Noise Waveforms based on Delay Observation in Inverter Chain Circuits 
Sub Title (in English)  
Keyword(1) power integrity design  
Keyword(2) power supply noise  
Keyword(3) power integrity  
Keyword(4) chip-pkg resonance  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Yutaka Uematsu  
1st Author's Affiliation Hitachi Co Ltd. (Hitachi Co Ltd.)
2nd Author's Name Hideki Osaka  
2nd Author's Affiliation Hitachi Co Ltd. (Hitachi Co Ltd.)
3rd Author's Name Eiichi Suzuki  
3rd Author's Affiliation Hitachi Co Ltd. (Hitachi Co Ltd.)
4th Author's Name Masayoshi Yagyu  
4th Author's Affiliation Hitachi Co Ltd. (Hitachi Co Ltd.)
5th Author's Name Tatsuya Saito  
5th Author's Affiliation Hitachi Co Ltd. (Hitachi Co Ltd.)
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Speaker Author-1 
Date Time 2009-11-20 13:55:00 
Presentation Time 25 minutes 
Registration for EMCJ 
Paper # EMCJ2009-83 
Volume (vol) vol.109 
Number (no) no.295 
Page pp.25-30 
#Pages 6 
Date of Issue 2009-11-13 (EMCJ) 

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