Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2009-12-02 16:00
[Panel Discussion] EMC Circuit Design and Jisso Design for System LSI -- Proposal for Circuit Design Managing EMC and Jisso Issue from Jisso-side --
Hideki Osaka (HITACHI Ltd.), Hideki Asai (Shizuoka Univ.), Hidefumi Ibe (HITACHI Ltd.), Yoshiyuki Saito (Panasonic), Takashi Harada (NEC), Narimasa Takahashi (IBM Japan) CPM2009-142 ICD2009-71
Abstract (in Japanese) (See Japanese page) 
(in English) Nowadays, a JISSO design is very important to get the target performance out of a system LSI. More specifically, co-design among chip, package and board is necessary in the point view of not only signal integrity, power integrity but also EMC (Electromagnetic Compatibility). This panel session is focused on and discussed about what the desirable chip design of system LSI and other semiconductor chips to get maximum performance with stable operation on the equipment or system loaded in the JISSO-side standpoint.
Keyword (in Japanese) (See Japanese page) 
(in English) System LSI / signal integrity / power integrity / Electromagnetic Compatibility / co-design / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 317, CPM2009-142, pp. 47-49, Dec. 2009.
Paper # CPM2009-142 
Date of Issue 2009-11-25 (CPM, ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPM2009-142 ICD2009-71

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2009-12-02 - 2009-12-04 
Place (in Japanese) (See Japanese page) 
Place (in English) Kochi City Culture-Plaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2009 ―New Field of VLSI Design― 
Paper Information
Registration To CPM 
Conference Code 2009-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) EMC Circuit Design and Jisso Design for System LSI 
Sub Title (in English) Proposal for Circuit Design Managing EMC and Jisso Issue from Jisso-side 
Keyword(1) System LSI  
Keyword(2) signal integrity  
Keyword(3) power integrity  
Keyword(4) Electromagnetic Compatibility  
Keyword(5) co-design  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Hideki Osaka  
1st Author's Affiliation HITACHI Limited (HITACHI Ltd.)
2nd Author's Name Hideki Asai  
2nd Author's Affiliation Shizuoka University (Shizuoka Univ.)
3rd Author's Name Hidefumi Ibe  
3rd Author's Affiliation HITACHI Limited (HITACHI Ltd.)
4th Author's Name Yoshiyuki Saito  
4th Author's Affiliation Panasonic (Panasonic)
5th Author's Name Takashi Harada  
5th Author's Affiliation NEC (NEC)
6th Author's Name Narimasa Takahashi  
6th Author's Affiliation IBM Japan (IBM Japan)
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2009-12-02 16:00:00 
Presentation Time 60 minutes 
Registration for CPM 
Paper # CPM2009-142, ICD2009-71 
Volume (vol) vol.109 
Number (no) no.317(CPM), no.318(ICD) 
Page pp.47-49 
#Pages 3 
Date of Issue 2009-11-25 (CPM, ICD) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan