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| Presentation | 2010-02-23 11:00 Compact Reconfigurable BDD Logic Circuits utilizing GaAs Nanowire Network Yuta Shiratori, Kensuke Miura (Hokkaido Univ.), Seiya Kasai (Hokkaido Univ./JST)  ED2009-208 SDM2009-205 Link to ES Tech. Rep. Archives: ED2009-208 SDM2009-205 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We describe a reconfigurable binary-decision-diagram logic circuit based on Shannon’s expansion of Boolean logic function and its graphical representation utilizing a semiconductor nanowire network. The circuit is reconfigured by using programmable switches that electrically connect and disconnect branches. This circuit has a compact structure with a small number of devices and a small circuit area compared with the conventional Si CMOS look-up table architecture. A two-input reconfigurable BDD circuit was fabricated on an etched GaAs nanowire network having hexagonal topology with Schottky wrap gates and SiN-based programmable switches. Its correct logic operation together with dynamic reconfiguration was successfully demonstrated. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Binary Decision Diagram (BDD) / GaAs Nanowire Network / Reconfigurable Logic Circuit / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 109, no. 422, ED2009-208, pp. 71-76, Feb. 2010. | |
| Paper # | ED2009-208 | |
| Date of Issue | 2010-02-15 (ED, SDM) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | ED2009-208 SDM2009-205 Link to ES Tech. Rep. Archives: ED2009-208 SDM2009-205 |
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| Conference Information | |
| Committee | ED SDM |
| Conference Date | 2010-02-22 - 2010-02-23 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawaken-Seinen-Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Functional Nano Device and Related Technology |
| Paper Information | |
| Registration To | ED |
| Conference Code | 2010-02-ED-SDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Compact Reconfigurable BDD Logic Circuits utilizing GaAs Nanowire Network |
| Sub Title (in English) | |
| Keyword(1) | Binary Decision Diagram (BDD) |
| Keyword(2) | GaAs Nanowire Network |
| Keyword(3) | Reconfigurable Logic Circuit |
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| 1st Author's Name | Yuta Shiratori |
| 1st Author's Affiliation | Hokkaido University (Hokkaido Univ.) |
| 2nd Author's Name | Kensuke Miura |
| 2nd Author's Affiliation | Hokkaido University (Hokkaido Univ.) |
| 3rd Author's Name | Seiya Kasai |
| 3rd Author's Affiliation | Hokkaido University/PRESTO JST (Hokkaido Univ./JST) |
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| Speaker | Author-1 |
| Date Time | 2010-02-23 11:00:00 |
| Presentation Time | 25 minutes |
| Registration for | ED |
| Paper # | ED2009-208, SDM2009-205 |
| Volume (vol) | vol.109 |
| Number (no) | no.422(ED), no.423(SDM) |
| Page | pp.71-76 |
| #Pages | 6 |
| Date of Issue | 2010-02-15 (ED, SDM) |
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