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Paper Abstract and Keywords
Presentation 2010-11-30 11:05
[Invited Talk] A wafer-level system integration technology for heterogeneous devices with pseudo-SoC
Hiroshi Yamada, Yutaka Onozuka, Atsuko Iida, Kazuhiko Itaya, Hideyuki Funaki (Toshiba R&D Center) CPM2010-135 ICD2010-94 Link to ES Tech. Rep. Archives: CPM2010-135 ICD2010-94
Abstract (in Japanese) (See Japanese page) 
(in English) A wafer level system integration technology for heterogeneous devices has been developed by applying pseudo-SOC.
The pseudo-SOC is designed to realize a single microchip with heterogeneous devices using individual processes, for epoxy resin, insulating layer, and redistribution layer, respectively. The KGD (Known Good Die) heterogeneous devices are embedded in the epoxy resin to reconfigure the reconfigured integration wafer. As the insulating layer and redistribution layer are formed by semiconductor wafer process without interposer substrate, the pseudo-SOC enables integration density as identical to that of SOC.
This paper presents an overview of wafer level system integration technology for heterogeneous devices by applied pseudo-SoC and then focuses on the flexible pseudo-SOC which integrates optical MEMS and its driver CMOS-LSI for mobile electronics device applications.
Keyword (in Japanese) (See Japanese page) 
(in English) Pseudo-SoC / Heterogeneous device / Wafer-level / System integration / Flexible / / /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 314, CPM2010-135, pp. 67-72, Nov. 2010.
Paper # CPM2010-135 
Date of Issue 2010-11-22 (CPM, ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPM2010-135 ICD2010-94 Link to ES Tech. Rep. Archives: CPM2010-135 ICD2010-94

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2010-11-29 - 2010-12-01 
Place (in Japanese) (See Japanese page) 
Place (in English) Kyushu University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2010 ―New Field of VLSI Design― 
Paper Information
Registration To CPM 
Conference Code 2010-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A wafer-level system integration technology for heterogeneous devices with pseudo-SoC 
Sub Title (in English)  
Keyword(1) Pseudo-SoC  
Keyword(2) Heterogeneous device  
Keyword(3) Wafer-level  
Keyword(4) System integration  
Keyword(5) Flexible  
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1st Author's Name Hiroshi Yamada  
1st Author's Affiliation Toshiba Corporation R&D Center (Toshiba R&D Center)
2nd Author's Name Yutaka Onozuka  
2nd Author's Affiliation Toshiba Corporation R&D Center (Toshiba R&D Center)
3rd Author's Name Atsuko Iida  
3rd Author's Affiliation Toshiba Corporation R&D Center (Toshiba R&D Center)
4th Author's Name Kazuhiko Itaya  
4th Author's Affiliation Toshiba Corporation R&D Center (Toshiba R&D Center)
5th Author's Name Hideyuki Funaki  
5th Author's Affiliation Toshiba Corporation R&D Center (Toshiba R&D Center)
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Speaker Author-1 
Date Time 2010-11-30 11:05:00 
Presentation Time 40 minutes 
Registration for CPM 
Paper # CPM2010-135, ICD2010-94 
Volume (vol) vol.110 
Number (no) no.314(CPM), no.315(ICD) 
Page pp.67-72 
#Pages
Date of Issue 2010-11-22 (CPM, ICD) 


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