Paper Abstract and Keywords |
Presentation |
2011-02-07 10:50
Path-finding for Integration of Robust Low-k (k-2.5) SiOCH in System LSI Naoya Inoue, Makoto Ueki, Hironori Yamamoto, Ippei Kume, Jun Kawahara, Manabu Iguchi, Hirokazu Honda, Yoshitaka Horikoshi, Yoshihiro Hayashi (Renesas Electronics Corp.) SDM2010-217 Link to ES Tech. Rep. Archives: SDM2010-217 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Impacts of k-value reduction on LSI performances are clarified quantitatively using 2M-gate net-list. Reduction in k-value from 3.0 to 2.5 for M2-M5 interconnect layers achieves 11%-drop in interconnect parasitic capacitance (Cint) and 8.4%-reduction in propagation delay (d), which also shrinks the effective variability of d to improve LSI operation margins. From a viewpoint of BEOL fabrication with k~2.5, a carbon-rich porous SiOCH film has high tolerance to process-induced damages, resulting in lower Cint than that of an O-rich film with similar k-value. Sustainability to FCBGA packaging with Pb-free solder bumps is also confirmed for the multi-level interconnects with the C-rich porous SiOCH. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
LSI / interconnect / low-k / capacitance / delay / damage / package / |
Reference Info. |
IEICE Tech. Rep., vol. 110, no. 408, SDM2010-217, pp. 7-12, Feb. 2011. |
Paper # |
SDM2010-217 |
Date of Issue |
2011-01-31 (SDM) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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SDM2010-217 Link to ES Tech. Rep. Archives: SDM2010-217 |