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Paper Abstract and Keywords
Presentation 2011-02-07 10:50
Path-finding for Integration of Robust Low-k (k-2.5) SiOCH in System LSI
Naoya Inoue, Makoto Ueki, Hironori Yamamoto, Ippei Kume, Jun Kawahara, Manabu Iguchi, Hirokazu Honda, Yoshitaka Horikoshi, Yoshihiro Hayashi (Renesas Electronics Corp.) SDM2010-217 Link to ES Tech. Rep. Archives: SDM2010-217
Abstract (in Japanese) (See Japanese page) 
(in English) Impacts of k-value reduction on LSI performances are clarified quantitatively using 2M-gate net-list. Reduction in k-value from 3.0 to 2.5 for M2-M5 interconnect layers achieves 11%-drop in interconnect parasitic capacitance (Cint) and 8.4%-reduction in propagation delay (d), which also shrinks the effective variability of d to improve LSI operation margins. From a viewpoint of BEOL fabrication with k~2.5, a carbon-rich porous SiOCH film has high tolerance to process-induced damages, resulting in lower Cint than that of an O-rich film with similar k-value. Sustainability to FCBGA packaging with Pb-free solder bumps is also confirmed for the multi-level interconnects with the C-rich porous SiOCH.
Keyword (in Japanese) (See Japanese page) 
(in English) LSI / interconnect / low-k / capacitance / delay / damage / package /  
Reference Info. IEICE Tech. Rep., vol. 110, no. 408, SDM2010-217, pp. 7-12, Feb. 2011.
Paper # SDM2010-217 
Date of Issue 2011-01-31 (SDM) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SDM2010-217 Link to ES Tech. Rep. Archives: SDM2010-217

Conference Information
Committee SDM  
Conference Date 2011-02-07 - 2011-02-07 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To SDM 
Conference Code 2011-02-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Path-finding for Integration of Robust Low-k (k-2.5) SiOCH in System LSI 
Sub Title (in English)  
Keyword(1) LSI  
Keyword(2) interconnect  
Keyword(3) low-k  
Keyword(4) capacitance  
Keyword(5) delay  
Keyword(6) damage  
Keyword(7) package  
Keyword(8)  
1st Author's Name Naoya Inoue  
1st Author's Affiliation Renesas Electronics Corporation (Renesas Electronics Corp.)
2nd Author's Name Makoto Ueki  
2nd Author's Affiliation Renesas Electronics Corporation (Renesas Electronics Corp.)
3rd Author's Name Hironori Yamamoto  
3rd Author's Affiliation Renesas Electronics Corporation (Renesas Electronics Corp.)
4th Author's Name Ippei Kume  
4th Author's Affiliation Renesas Electronics Corporation (Renesas Electronics Corp.)
5th Author's Name Jun Kawahara  
5th Author's Affiliation Renesas Electronics Corporation (Renesas Electronics Corp.)
6th Author's Name Manabu Iguchi  
6th Author's Affiliation Renesas Electronics Corporation (Renesas Electronics Corp.)
7th Author's Name Hirokazu Honda  
7th Author's Affiliation Renesas Electronics Corporation (Renesas Electronics Corp.)
8th Author's Name Yoshitaka Horikoshi  
8th Author's Affiliation Renesas Electronics Corporation (Renesas Electronics Corp.)
9th Author's Name Yoshihiro Hayashi  
9th Author's Affiliation Renesas Electronics Corporation (Renesas Electronics Corp.)
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Speaker Author-1 
Date Time 2011-02-07 10:50:00 
Presentation Time 30 minutes 
Registration for SDM 
Paper # SDM2010-217 
Volume (vol) vol.110 
Number (no) no.408 
Page pp.7-12 
#Pages
Date of Issue 2011-01-31 (SDM) 


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