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Paper Abstract and Keywords
Presentation 2018-03-07 15:45
Minimizing End-to-end Latency in Circuit-switched Network for Parallel Computers
Yao Hu, Shoichi Hirasawa, Michihiro Koibuchi (NII) CPSY2017-135 DC2017-91
Abstract (in Japanese) (See Japanese page) 
(in English) Network congestion usually leads to increased communication time in supercomputer and datacenter networks. In our previous study, we have proposed an electrical circuit-switched (ECS) network to avoid network congestion and guarantee a certain amount of bandwidth for each communication pair, which makes its end-to-end latency predictable. In this report, we discuss several methods to minimize end-to-end latency in our ECS network. Through numerical analysis, we get upper and lower bounds of the end-to-end latency for one communication in the network and infer conditions of the minimum end-to-end latency. We thus come up with two methods to reach or approach the minimum latency: routing update and sending time slot adjustment. Furthermore, we design a hybrid CS/PS switch which takes both advantages of circuit switching and packet switching and also helps to reduce the minimum necessary number of slots for each switch in the network. Evaluation results show that our ECS network can obtain large benefits from complement of a small packet switching component.
Keyword (in Japanese) (See Japanese page) 
(in English) datacenter network / end-to-end latency / circuit switching / packet switching / / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 479, CPSY2017-135, pp. 95-100, March 2018.
Paper # CPSY2017-135 
Date of Issue 2018-02-28 (CPSY, DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Conference Date 2018-03-07 - 2018-03-08 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinoshima Bunka-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) ETNET2018 
Paper Information
Registration To CPSY 
Conference Code 2018-03-CPSY-DC-SLDM-EMB-ARC 
Language English (Japanese title is available) 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Minimizing End-to-end Latency in Circuit-switched Network for Parallel Computers 
Sub Title (in English)  
Keyword(1) datacenter network  
Keyword(2) end-to-end latency  
Keyword(3) circuit switching  
Keyword(4) packet switching  
1st Author's Name Yao Hu  
1st Author's Affiliation National Institute of Informatics (NII)
2nd Author's Name Shoichi Hirasawa  
2nd Author's Affiliation National Institute of Informatics (NII)
3rd Author's Name Michihiro Koibuchi  
3rd Author's Affiliation National Institute of Informatics (NII)
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Date Time 2018-03-07 15:45:00 
Presentation Time 25 
Registration for CPSY 
Paper # CPSY2017-135, DC2017-91 
Volume (vol) 117 
Number (no) no.479(CPSY), no.480(DC) 
Page pp.95-100 
Date of Issue 2018-02-28 (CPSY, DC) 

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