Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2022-01-24 11:25
FPGA Implementation of Scalable Fully Coupled Annealing Processing Sysytem by Using Multi-chip Operation
Kaoru Yamamoto, Takayuki Kawahara (TUS) VLD2021-53 CPSY2021-22 RECONF2021-61
Abstract (in Japanese) (See Japanese page) 
(in English) Annealing machines can be classified into sparsely coupled types and fully coupled types. The fully coupled type has the advantage that the combinatorial optimization problem can be easily mapped to the Annealing machine and the number of problems that can be solved to the number of spins is larger than that of the sparsely coupled type. However, it has the disadvantage that it is difficult to expand the number of spins due to the complexity of the existence of a connection between all spins. In particular, it is difficult to expand by the multi-chip operation already proposed in the sparsely coupled types. In this paper, We proposed the architecture of a fully coupled annealing machine that performs the multi-chip operation by dividing it into two types: chip① performs calculations, and chip② updates a spin value and connects between all chips on the system. It is implemented and verified on an actual FPGA board. In addition, to improve the parallelism of this annealing machine and multi-chip operation, we implemented parallel annealing operation by multi-chip and verified and compared the accuracy. As a result, the accuracy of the solution improved and the average value of the solution improved by about 4.9%.
Keyword (in Japanese) (See Japanese page) 
(in English) Annealing Processer / Simulated Aneealing / FPGA / Multi-chip operation / Ising Model / / /  
Reference Info. IEICE Tech. Rep., vol. 121, no. 343, CPSY2021-22, pp. 25-30, Jan. 2022.
Paper # CPSY2021-22 
Date of Issue 2022-01-17 (VLD, CPSY, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2021-53 CPSY2021-22 RECONF2021-61

Conference Information
Committee RECONF VLD CPSY IPSJ-ARC IPSJ-SLDM  
Conference Date 2022-01-24 - 2022-01-25 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc. 
Paper Information
Registration To CPSY 
Conference Code 2022-01-RECONF-VLD-CPSY-ARC-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) FPGA Implementation of Scalable Fully Coupled Annealing Processing Sysytem by Using Multi-chip Operation 
Sub Title (in English)  
Keyword(1) Annealing Processer  
Keyword(2) Simulated Aneealing  
Keyword(3) FPGA  
Keyword(4) Multi-chip operation  
Keyword(5) Ising Model  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Kaoru Yamamoto  
1st Author's Affiliation Tokyo University of Science (TUS)
2nd Author's Name Takayuki Kawahara  
2nd Author's Affiliation Tokyo University of Science (TUS)
3rd Author's Name  
3rd Author's Affiliation ()
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2022-01-24 11:25:00 
Presentation Time 25 minutes 
Registration for CPSY 
Paper # VLD2021-53, CPSY2021-22, RECONF2021-61 
Volume (vol) vol.121 
Number (no) no.342(VLD), no.343(CPSY), no.344(RECONF) 
Page pp.25-30 
#Pages 6 
Date of Issue 2022-01-17 (VLD, CPSY, RECONF) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan