IEICE Technical Committee Submission System
Advance Program
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top  Go Back   / [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 

Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Kazutoshi Kobayashi (Kyoto Inst. of Tech.)
Vice Chair Minako Ikeda (NTT)
Secretary Daisuke Kanemoto (Osaka Univ.), Makoto Miyamura (NEC)

Technical Committee on Computer Systems (CPSY) [schedule] [select]
Chair Michihiro Koibuchi (NII)
Vice Chair Kota Nakajima (Fujitsu Lab.), Tomoaki Tsumura (Nagoya Inst. of Tech.)
Secretary Yasushi Inoguchi (JAIST), Shugo Ogawa (Hitachi)
Assistant Ryohei Kobayashi (Tsukuba Univ.), Takaaki Miyajima (Meiji Univ.)

Technical Committee on Reconfigurable Systems (RECONF) [schedule] [select]
Chair Kentaro Sano (RIKEN)
Vice Chair Yoshiki Yamaguchi (Tsukuba Univ.), Tomonori Izumi (Ritsumeikan Univ.)
Secretary Yuuki Kobayashi (NEC), Hiroki Nakahara (Tokyo Inst. of Tech.)
Assistant Yukitaka Takemura (INTEL), Yasunori Osana (Ryukyu Univ.)

Special Interest Group on System Architecture (IPSJ-ARC) [schedule] [select]
Chair Hiroshi Inoue (Kyushu Univ.)
Secretary Masaaki Kondo (Univ. of Tokyo), Ryota Shioya (Nagoya Univ.), Miho Tanaka (Fujitsu Labs.), Yohei Hasegawa (Toshiba Memory)

Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [schedule] [select]
Chair Yuichi Nakamura (NEC)
Secretary Kenshu Seto (Tokyo City Univ.), Kazushi Kawamura (Tokyo Inst. of Tech.), Masayuki Hiromoto (Fujitsu), Hiroki Hosoda (Sony LSI Design)

Conference Date Mon, Jan 24, 2022 09:30 - 17:35
Tue, Jan 25, 2022 09:30 - 17:30
Topics FPGA Applications, etc. 
Conference Place Online 
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Registration Fee This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on RECONF, VLD, CPSY.

Mon, Jan 24 AM 
09:30 - 11:10
09:30-09:55 Study on a Correlation Controlling Method to Realize Correlation-used Calculations Sequentially in Stochastic Computing VLD2021-49 CPSY2021-18 RECONF2021-57 Shu Zhang, Shigeru Yamashita (Ritsumeikan Univ.)
09:55-10:20 Study on Reverse Converters for RNS moduli set {2^k,2^n+1,2^n-1} using Signed-Digit numbers VLD2021-50 CPSY2021-19 RECONF2021-58 Takahiro Morii, Yuuki Tanaka, Shugang Wei (Gunma Univ.)
10:20-10:45 Full Hardware Implementation of RTOS-Based Systems Using General-Purpose High-Level Synthesizer VLD2021-51 CPSY2021-20 RECONF2021-59 Takuya Ando, Yugo Ishii, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO)
10:45-11:10 Design of Inter-Task Communication Modules for Full Hardware Implementation of RTOS-Based Systems VLD2021-52 CPSY2021-21 RECONF2021-60 Yukino Shinohara, Nagisa Ishiura (Kwansei Gakuin Univ.)
  11:10-11:25 Break ( 15 min. )
Mon, Jan 24 AM 
11:25 - 12:15
11:25-11:50 FPGA Implementation of Scalable Fully Coupled Annealing Processing Sysytem by Using Multi-chip Operation VLD2021-53 CPSY2021-22 RECONF2021-61 Kaoru Yamamoto, Takayuki Kawahara (TUS)
11:50-12:15 Multi-spin-flip method for Ising machines and its application VLD2021-54 CPSY2021-23 RECONF2021-62 Tatsuhiko Shirai, Nozomu Tagawa (Waseda Univ.)
  12:15-13:15 Break ( 60 min. )
Mon, Jan 24 PM 
13:15 - 14:05
13:15-14:05 [Invited Talk]
A Challenge of Research, Development, Manufacturing, and Marketing of Quantum Computing Control Systems VLD2021-55 CPSY2021-24 RECONF2021-63
Takefumi Miyoshi (QuEL, Inc./e-trees.Japan, Inc./Osaka Univ.)
  14:05-14:25 Break ( 20 min. )
Mon, Jan 24 PM 
14:25 - 15:40
14:25-14:50 VLD2021-56 CPSY2021-25 RECONF2021-64 ()
14:50-15:15 Implementation of a RISC-V SMT Core in Virtual Engine Architecture VLD2021-57 CPSY2021-26 RECONF2021-65 Hidetaro Tanaka, Tomoaki Tanaka, Keita Nagaoka, Ryosuke Higashi (TUAT), Tsutomu Sekibe, Shuichi Takada (ArchiTek), Hironori Nakajo (TUAT)
(10) 15:15-15:40  
  15:40-15:55 Break ( 15 min. )
Mon, Jan 24 PM 
15:55 - 17:35
15:55-16:20 Accelerating Deep Neural Networks on Edge Devices by Knowledge Distillation and Layer Pruning VLD2021-58 CPSY2021-27 RECONF2021-66 Yuki Ichikawa, Akira Jinguji, Ryosuke Kuramochi, Hiroki Nakahara (Titech)
16:20-16:45 Addition of DPU Training Function by Tail Layer Training VLD2021-59 CPSY2021-28 RECONF2021-67 Yuki Takashima, Akira Jinguji, Hiroki Nakahara (Tokyo Tech)
16:45-17:10 A study of an accelerator for CNN inference on FPGA clusters VLD2021-60 CPSY2021-29 RECONF2021-68 Rintaro Sakai (Kumamoto Univ. /R-CSS), Yasuhiro Nakahara (Kumamoto Univ. /R-CCS), Kentaro Sano (R-CCS), Masahiro Iida (Kumamoto Univ. /R-CCS)
17:10-17:35 Ternarizing Deep Spiking Neural Network VLD2021-61 CPSY2021-30 RECONF2021-69 Man Wu, Yirong Kan, Van_Tinh Nguyen, Renyuan Zhang, Yasuhiko Nakashima (NAIST)
  17:35-18:00 Break ( 25 min. )
  18:00-20:00 Online Banquet ( 120 min. )
Tue, Jan 25 AM 
09:30 - 11:10
09:30-09:55 GPU acceleration of algorithm for minimal distance approximate calculation between two objects VLD2021-62 CPSY2021-31 RECONF2021-70 Masumi Fukuta, Takakazu Kurokawa, Takashi Matsubara, Keisuke Iwai (NDA)
09:55-10:20 An Accuracy-Aware Data Size Reduction Method of 3D Lidar SLAM VLD2021-63 CPSY2021-32 RECONF2021-71 Ryuto Kojima, Keisuke Sugiura, Hiroki Matsutani (Keio Univ.)
10:20-10:45 FPGA Implementation of Radar Imaging for Walk-Through Security Screening System VLD2021-64 CPSY2021-33 RECONF2021-72 Tatsuya Sumiya, Yuki Kobayashi, Masayuki Ariyoshi (NEC)
10:45-11:10 An Implementation of a Real-time Stereo Matching System on FPGA VLD2021-65 CPSY2021-34 RECONF2021-73 Kaijie Wei (Keio Univ.), Yuki Kuno (Marelli Corp.), Masatoshi Arai (Saitama Univ.), Hideharu Amano (Keio Univ.)
  11:10-11:25 Break ( 15 min. )
Tue, Jan 25 AM 
11:25 - 12:15
11:25-11:50 A Light-Weight Machine Learning based Packet Routing using Online Sequential Learning VLD2021-66 CPSY2021-35 RECONF2021-74 Kenji Nemoto, Masaki Furukawa, Hirohisa Watanabe, Hiroki Matsutani (Keio Univ.)
11:50-12:15 VLD2021-67 CPSY2021-36 RECONF2021-75
  12:15-13:15 Break ( 60 min. )
Tue, Jan 25 PM 
13:15 - 14:30
13:15-13:40 A Study on Technology mapping method for Scalable Logic Module VLD2021-68 CPSY2021-37 RECONF2021-76 Izumi Kiuchi, Yuya Nakazato (Kumamoto Univ.), Qian Zhao (KIT), Masahiro Iida (Kumamoto Univ.)
(22) 13:40-14:05  
14:05-14:30 Initial Design and Evaluation of RIKEN CGRA: Data-Driven Architecture for Future HPC VLD2021-71 CPSY2021-40 RECONF2021-79 Boma Adhi, Carlos Cortes, Yiyu Tan (R-CCS), Takuya Kojima (Tokyo Univ.), Artur Podobas (KTH), Kentaro Sano (R-CCS)
  14:30-14:45 Break ( 15 min. )
Tue, Jan 25 PM 
14:45 - 16:25
14:45-15:10 A Preliminary Evaluation of a Compiler for RIKEN CGRA in HPC VLD2021-69 CPSY2021-38 RECONF2021-77 Takuya Kojima (U.Tokyo), Carlos Cesar Cortes Torres, Boma Adhi, Yiyu Tan, Kentaro Sano (RIKEN)
15:10-15:35 VLD2021-70 CPSY2021-39 RECONF2021-78
15:35-16:00 Preliminary evaluation of cache coherent interconnect for Reconfigurable Virtual Accelerator (ReVA) VLD2021-72 CPSY2021-41 RECONF2021-80 Eriko Maeda, Daichi Teruya, Hironori Nakajo (TUAT)
16:00-16:25 Design of a Quadruple Precision Floating-Point Arithmetic Unit for FPGAs and its Evaluation by Conjugate Gradient Method VLD2021-73 CPSY2021-42 RECONF2021-81 Naoki Kakine, Atsushi Kubota, Tetsuo Hironaka (Hiroshima City Univ)
  16:25-16:40 Break ( 15 min. )
Tue, Jan 25 PM 
16:40 - 17:30
16:40-17:05 Testing of Optimization Performance of Android DEX Compilers Based on Native Code Comparison VLD2021-74 CPSY2021-43 RECONF2021-82 Naoki Yoshida, Nagisa Ishiura (Kwansei Gakuin Univ.)
17:05-17:30 Hard-to-Detect Hardware Trojan Attack Exploiting Coherence Control Mechanisms VLD2021-75 CPSY2021-44 RECONF2021-83 Yoshiya Shikama (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Daisuke KANEMOTO (Osaka Univ.)
E--mail: deeieng-u 
Announcement See also VLD's homepage:
CPSY Technical Committee on Computer Systems (CPSY)   [Latest Schedule]
Contact Address CPSY WEB 
RECONF Technical Committee on Reconfigurable Systems (RECONF)   [Latest Schedule]
Contact Address Hiroki Nakahara (Tokyo Inst. of Tech.)
Yuki Kobayashi (NEC)
E--mail: y-bahqc 
IPSJ-ARC Special Interest Group on System Architecture (IPSJ-ARC)   [Latest Schedule]
Contact Address  
IPSJ-SLDM Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)   [Latest Schedule]
Contact Address Kenshu Seto (Tokyo City University)
E--mail: ktcu 
Announcement Please see the IPSJ-SLDM page below:

Last modified: 2022-01-14 08:40:45

Notification: Mail addresses are partially hidden against SPAM.

[Download Paper's Information (in Japanese)] <-- Press download button after click here.
[Cover and Index of IEICE Technical Report by Issue]

[Presentation and Participation FAQ] (in Japanese)

[Return to VLD Schedule Page]   /   [Return to CPSY Schedule Page]   /   [Return to RECONF Schedule Page]   /   [Return to IPSJ-ARC Schedule Page]   /   [Return to IPSJ-SLDM Schedule Page]   /  
 Go Top  Go Back   / [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 

[Return to Top Page]

[Return to IEICE Web Page]

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan