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Paper Abstract and Keywords
Presentation 2022-01-24 10:20
Full Hardware Implementation of RTOS-Based Systems Using General-Purpose High-Level Synthesizer
Takuya Ando, Yugo Ishii, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) VLD2021-51 CPSY2021-20 RECONF2021-59
Abstract (in Japanese) (See Japanese page) 
(in English) This article proposes a method for implementing a whole RTOS-based system as hardware using general-purpose high-level synthesizer. Muguruma has proposed a scheme where both all the tasks/handlers and all the RTOS functions are implemented as hardware. However, it assumes the use of a dedicated binary synthesizer, ACAP, where generated task modules have stall ports for suspending their execution and accesses to globally shared variables are realized as loads/stores using automatically generated addresses, which are not necessarily possible by general high-level synthesizers. This paper proposes a method where execution of tasks is controlled by allowing/disabling execution of service calls from the tasks, and code transformation using a wrapper class for shared variable accesses and functions within a function, to make general high-level synthesizers applicable to the full-hardware scheme. Based on the proposed methods, a hardware module for a reduced version of sample1 bundled with TOPPERS/ASP has been successfully implemented as hardware using Xilinx Vitis HLS, where the size of the resulting circuit was substantially smaller than that by the previous method.
Keyword (in Japanese) (See Japanese page) 
(in English) Real-Time Systems / RTOS / System Synthesis / Hardware Accelerator / TOPPERS/ASP3 / High-Level Synthesis / /  
Reference Info. IEICE Tech. Rep., vol. 121, no. 342, VLD2021-51, pp. 13-18, Jan. 2022.
Paper # VLD2021-51 
Date of Issue 2022-01-17 (VLD, CPSY, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2021-51 CPSY2021-20 RECONF2021-59

Conference Information
Committee RECONF VLD CPSY IPSJ-ARC IPSJ-SLDM  
Conference Date 2022-01-24 - 2022-01-25 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc. 
Paper Information
Registration To VLD 
Conference Code 2022-01-RECONF-VLD-CPSY-ARC-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Full Hardware Implementation of RTOS-Based Systems Using General-Purpose High-Level Synthesizer 
Sub Title (in English)  
Keyword(1) Real-Time Systems  
Keyword(2) RTOS  
Keyword(3) System Synthesis  
Keyword(4) Hardware Accelerator  
Keyword(5) TOPPERS/ASP3  
Keyword(6) High-Level Synthesis  
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Keyword(8)  
1st Author's Name Takuya Ando  
1st Author's Affiliation Kwansei Gakuin University (Kwansei Gakuin Univ.)
2nd Author's Name Yugo Ishii  
2nd Author's Affiliation Kwansei Gakuin University (Kwansei Gakuin Univ.)
3rd Author's Name Nagisa Ishiura  
3rd Author's Affiliation Kwansei Gakuin University (Kwansei Gakuin Univ.)
4th Author's Name Hiroyuki Tomiyama  
4th Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
5th Author's Name Hiroyuki Kanbara  
5th Author's Affiliation Advanced Science, Technology & Management Research Institute of KYOTO (ASTEM RI/KYOTO)
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Speaker Author-1 
Date Time 2022-01-24 10:20:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2021-51, CPSY2021-20, RECONF2021-59 
Volume (vol) vol.121 
Number (no) no.342(VLD), no.343(CPSY), no.344(RECONF) 
Page pp.13-18 
#Pages 6 
Date of Issue 2022-01-17 (VLD, CPSY, RECONF) 

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