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Paper Abstract and Keywords
Presentation 2022-01-24 14:50
Implementation of a RISC-V SMT Core in Virtual Engine Architecture
Hidetaro Tanaka, Tomoaki Tanaka, Keita Nagaoka, Ryosuke Higashi (TUAT), Tsutomu Sekibe, Shuichi Takada (ArchiTek), Hironori Nakajo (TUAT) VLD2021-57 CPSY2021-26 RECONF2021-65
Abstract (in Japanese) (See Japanese page) 
(in English) The RISC-V core which supports simultaneous multithreading (SMT) on a heterogeneous virtual engine architecture has been implemented. In the arcitecture multiple types of engines which are specialized for different purposes are conducted. As the advantage of SMT, the RISC-V SMT core allows multiple threads to be executed simultaneously at a lower cost than simply using multiple cores. The RISC-V core supports operations of other engines under the SMT mechanism in order to be installed in ”Chichibu” which is developed by ArchiTek as a multicore chip for edge AI. In this implementation, we have reduced the hardware resource usage to less than half of the previous implementation. Also the IPC has been improved by about 3% to 6% by using SMT even when delays in instruction and data memory is brought.
Keyword (in Japanese) (See Japanese page) 
(in English) RISC-V / Simultaneous Multithreading / AI / Heterogeneous Processor / / / /  
Reference Info. IEICE Tech. Rep., vol. 121, no. 344, RECONF2021-65, pp. 43-48, Jan. 2022.
Paper # RECONF2021-65 
Date of Issue 2022-01-17 (VLD, CPSY, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2021-57 CPSY2021-26 RECONF2021-65

Conference Information
Committee RECONF VLD CPSY IPSJ-ARC IPSJ-SLDM  
Conference Date 2022-01-24 - 2022-01-25 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc. 
Paper Information
Registration To RECONF 
Conference Code 2022-01-RECONF-VLD-CPSY-ARC-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Implementation of a RISC-V SMT Core in Virtual Engine Architecture 
Sub Title (in English)  
Keyword(1) RISC-V  
Keyword(2) Simultaneous Multithreading  
Keyword(3) AI  
Keyword(4) Heterogeneous Processor  
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1st Author's Name Hidetaro Tanaka  
1st Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
2nd Author's Name Tomoaki Tanaka  
2nd Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
3rd Author's Name Keita Nagaoka  
3rd Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
4th Author's Name Ryosuke Higashi  
4th Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
5th Author's Name Tsutomu Sekibe  
5th Author's Affiliation ArchiTek Corporation (ArchiTek)
6th Author's Name Shuichi Takada  
6th Author's Affiliation ArchiTek Corporation (ArchiTek)
7th Author's Name Hironori Nakajo  
7th Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
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Speaker Author-1 
Date Time 2022-01-24 14:50:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2021-57, CPSY2021-26, RECONF2021-65 
Volume (vol) vol.121 
Number (no) no.342(VLD), no.343(CPSY), no.344(RECONF) 
Page pp.43-48 
#Pages 6 
Date of Issue 2022-01-17 (VLD, CPSY, RECONF) 

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