Paper Abstract and Keywords |
Presentation |
2022-01-24 14:50
Implementation of a RISC-V SMT Core in Virtual Engine Architecture Hidetaro Tanaka, Tomoaki Tanaka, Keita Nagaoka, Ryosuke Higashi (TUAT), Tsutomu Sekibe, Shuichi Takada (ArchiTek), Hironori Nakajo (TUAT) VLD2021-57 CPSY2021-26 RECONF2021-65 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
The RISC-V core which supports simultaneous multithreading (SMT) on a heterogeneous virtual engine architecture has been implemented. In the arcitecture multiple types of engines which are specialized for different purposes are conducted. As the advantage of SMT, the RISC-V SMT core allows multiple threads to be executed simultaneously at a lower cost than simply using multiple cores. The RISC-V core supports operations of other engines under the SMT mechanism in order to be installed in ”Chichibu” which is developed by ArchiTek as a multicore chip for edge AI. In this implementation, we have reduced the hardware resource usage to less than half of the previous implementation. Also the IPC has been improved by about 3% to 6% by using SMT even when delays in instruction and data memory is brought. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
RISC-V / Simultaneous Multithreading / AI / Heterogeneous Processor / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 121, no. 344, RECONF2021-65, pp. 43-48, Jan. 2022. |
Paper # |
RECONF2021-65 |
Date of Issue |
2022-01-17 (VLD, CPSY, RECONF) |
ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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VLD2021-57 CPSY2021-26 RECONF2021-65 |
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