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Paper Abstract and Keywords
Presentation 2022-01-24 16:45
A study of an accelerator for CNN inference on FPGA clusters
Rintaro Sakai (Kumamoto Univ. /R-CSS), Yasuhiro Nakahara (Kumamoto Univ. /R-CCS), Kentaro Sano (R-CCS), Masahiro Iida (Kumamoto Univ. /R-CCS) VLD2021-60 CPSY2021-29 RECONF2021-68
Abstract (in Japanese) (See Japanese page) 
(in English) In this study, we propose a CNN accelerator for FPGA clusters, which accelerates the CNN inference process by distributing and parallelizing it to each FPGA. As a preliminary evaluation of CNN inference performance in FPGA clusters, we evaluate the stand-alone performance of the architecture of the CNN accelerator for FPGAs, and also evaluate the performance when the CNN processing is divided among multiple FPGAs. This architecture is developed based on our previously proposed reconfigurable AI chip, ReNA. By optimizing this architecture for FPGAs, we found that the inference performance of FPGAs is improved: the CNN throughput increased by 64% compared to the pre-optimization level. By dividing CNN processing among multiple FPGAs, parallelization efficiency can be kept at a maximum of 90% even when the number of FPGAs increases to 16.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / CNN / / / / / /  
Reference Info. IEICE Tech. Rep., vol. 121, no. 344, RECONF2021-68, pp. 61-66, Jan. 2022.
Paper # RECONF2021-68 
Date of Issue 2022-01-17 (VLD, CPSY, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2021-60 CPSY2021-29 RECONF2021-68

Conference Information
Committee RECONF VLD CPSY IPSJ-ARC IPSJ-SLDM  
Conference Date 2022-01-24 - 2022-01-25 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc. 
Paper Information
Registration To RECONF 
Conference Code 2022-01-RECONF-VLD-CPSY-ARC-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A study of an accelerator for CNN inference on FPGA clusters 
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Keyword(1) FPGA  
Keyword(2) CNN  
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1st Author's Name Rintaro Sakai  
1st Author's Affiliation Kumamoto University/RIKEN Center for Computational Science (Kumamoto Univ. /R-CSS)
2nd Author's Name Yasuhiro Nakahara  
2nd Author's Affiliation Kumamoto University/RIKEN Center for Computational Science (Kumamoto Univ. /R-CCS)
3rd Author's Name Kentaro Sano  
3rd Author's Affiliation RIKEN Center for Computational Science (R-CCS)
4th Author's Name Masahiro Iida  
4th Author's Affiliation Kumamoto University/RIKEN Center for Computational Science (Kumamoto Univ. /R-CCS)
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Speaker Author-1 
Date Time 2022-01-24 16:45:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2021-60, CPSY2021-29, RECONF2021-68 
Volume (vol) vol.121 
Number (no) no.342(VLD), no.343(CPSY), no.344(RECONF) 
Page pp.61-66 
#Pages 6 
Date of Issue 2022-01-17 (VLD, CPSY, RECONF) 

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