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Paper Abstract and Keywords
Presentation 2022-01-24 10:45
Design of Inter-Task Communication Modules for Full Hardware Implementation of RTOS-Based Systems
Yukino Shinohara, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2021-52 CPSY2021-21 RECONF2021-60
Abstract (in Japanese) (See Japanese page) 
(in English) This paper presents hardware implementation of inter-task communication functions of RTOS, in the scheme where all the tasks/handlers along with all the RTOS services are implemented as hardware.
Hardware modules for the data queue and the message buffer for Muguruma's architecture are designed.
The proposed data queue design maintains multiple data queues in a single module and processes send/receive operations including handling of task waiting and timeouts efficiently in cooperation with the hardware module to manage task execution.
The message buffer module also manages multiple message buffers and arranges the transfer of variable length message data via a dedicated register between the message buffer module and each task module.
The designed data queue takes only 3 cycles for a send/receive operation, and the message buffer processes send/receive of a message of $n$ bytes within $n+8$ cycles.
Keyword (in Japanese) (See Japanese page) 
(in English) Real-Time Systems / RTOS / System Synthesis / Hardware Accelerator / TOPPERS/ASP3 / FreeRTOS / High-Level Synthesis /  
Reference Info. IEICE Tech. Rep., vol. 121, no. 342, VLD2021-52, pp. 19-24, Jan. 2022.
Paper # VLD2021-52 
Date of Issue 2022-01-17 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2021-52 CPSY2021-21 RECONF2021-60

Conference Information
Conference Date 2022-01-24 - 2022-01-25 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc. 
Paper Information
Registration To VLD 
Conference Code 2022-01-RECONF-VLD-CPSY-ARC-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design of Inter-Task Communication Modules for Full Hardware Implementation of RTOS-Based Systems 
Sub Title (in English)  
Keyword(1) Real-Time Systems  
Keyword(2) RTOS  
Keyword(3) System Synthesis  
Keyword(4) Hardware Accelerator  
Keyword(5) TOPPERS/ASP3  
Keyword(6) FreeRTOS  
Keyword(7) High-Level Synthesis  
1st Author's Name Yukino Shinohara  
1st Author's Affiliation Kwansei Gakuin University (Kwansei Gakuin Univ.)
2nd Author's Name Nagisa Ishiura  
2nd Author's Affiliation Kwansei Gakuin University (Kwansei Gakuin Univ.)
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Speaker Author-1 
Date Time 2022-01-24 10:45:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2021-52, CPSY2021-21, RECONF2021-60 
Volume (vol) vol.121 
Number (no) no.342(VLD), no.343(CPSY), no.344(RECONF) 
Page pp.19-24 
Date of Issue 2022-01-17 (VLD, CPSY, RECONF) 

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