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Paper Abstract and Keywords
Presentation 2022-01-25 13:15
A Study on Technology mapping method for Scalable Logic Module
Izumi Kiuchi, Yuya Nakazato (Kumamoto Univ.), Qian Zhao (KIT), Masahiro Iida (Kumamoto Univ.) VLD2021-68 CPSY2021-37 RECONF2021-76
Abstract (in Japanese) (See Japanese page) 
(in English) The LUT (Lookup Table) , which is widely used as the logic cell in FPGA (Field Programmable Gate Array), can implement any logic function, but it has a drawback that its memory increases exponentially as the number of inputs increases. SLM (Scalable Logic Module) is a logic cell with a hierarchical structure using Shannon's expansion, which saves memory compared to the LUT for the same number of inputs. However, SLMs tend to increase the number of logic cells after technology mapping compared to LUTs due to the limitation of implementable logic functions. In this study, we focus on the characteristics of logic functions that can be implemented in SLMs, and propose a cut ``iCut'' that can be implemented in SLMs and can be globally barred. The iCut is a $K$ input cut obtained by merging the trivial cut of one fan-in node with the $K-1$ input cut, which is the cut of another fan-in node at a node. In technology mapping, we combine the cut search of the proposed iCut with existing methods. As a result, the number of logical cells was reduced by up to 7.8% when compared with the existing method.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / Logic Cell / SLM / Technology Mapping / / / /  
Reference Info. IEICE Tech. Rep., vol. 121, no. 344, RECONF2021-76, pp. 108-113, Jan. 2022.
Paper # RECONF2021-76 
Date of Issue 2022-01-17 (VLD, CPSY, RECONF) 
ISSN Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2021-68 CPSY2021-37 RECONF2021-76

Conference Information
Committee RECONF VLD CPSY IPSJ-ARC IPSJ-SLDM  
Conference Date 2022-01-24 - 2022-01-25 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc. 
Paper Information
Registration To RECONF 
Conference Code 2022-01-RECONF-VLD-CPSY-ARC-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Study on Technology mapping method for Scalable Logic Module 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) Logic Cell  
Keyword(3) SLM  
Keyword(4) Technology Mapping  
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1st Author's Name Izumi Kiuchi  
1st Author's Affiliation Kumamoto University (Kumamoto Univ.)
2nd Author's Name Yuya Nakazato  
2nd Author's Affiliation Kumamoto University (Kumamoto Univ.)
3rd Author's Name Qian Zhao  
3rd Author's Affiliation Kyushu Institute of Technology (KIT)
4th Author's Name Masahiro Iida  
4th Author's Affiliation Kumamoto University (Kumamoto Univ.)
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Speaker Author-1 
Date Time 2022-01-25 13:15:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2021-68, CPSY2021-37, RECONF2021-76 
Volume (vol) vol.121 
Number (no) no.342(VLD), no.343(CPSY), no.344(RECONF) 
Page pp.108-113 
#Pages
Date of Issue 2022-01-17 (VLD, CPSY, RECONF) 


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