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| Paper Abstract and Keywords | ||
| Presentation | 2022-01-25 15:35 Preliminary evaluation of cache coherent interconnect for Reconfigurable Virtual Accelerator (ReVA) Eriko Maeda, Daichi Teruya, Hironori Nakajo (TUAT)  VLD2021-72 CPSY2021-41 RECONF2021-80 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In recent years, the amount of computation and data in HPC, AI, and other computational processing has become increasingly large, and hardware acceleration has become an issue of insufficient resources and complex accelerator configurations. The authors have presented the concept of Reconfigurable Virtual Accelerator (ReVA) in the past. However, it was not easy to realize the interconnect and coherence processing for DSM implementation. In this paper, we focus on CXL (Compute Express Link), which is a cache-coherent interconnect standard. We propose ReVA again using CXL and study its feasibility. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | FPGA / hardware acceleration / HLS / CXL / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 121, no. 344, RECONF2021-80, pp. 132-137, Jan. 2022. | |
| Paper # | RECONF2021-80 | |
| Date of Issue | 2022-01-17 (VLD, CPSY, RECONF) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2021-72 CPSY2021-41 RECONF2021-80 |
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| Conference Information | |
| Committee | RECONF VLD CPSY IPSJ-ARC IPSJ-SLDM |
| Conference Date | 2022-01-24 - 2022-01-25 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc. |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2022-01-RECONF-VLD-CPSY-ARC-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Preliminary evaluation of cache coherent interconnect for Reconfigurable Virtual Accelerator (ReVA) |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | hardware acceleration |
| Keyword(3) | HLS |
| Keyword(4) | CXL |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Eriko Maeda |
| 1st Author's Affiliation | Tokyo University of Agriculture and Technology (TUAT) |
| 2nd Author's Name | Daichi Teruya |
| 2nd Author's Affiliation | Tokyo University of Agriculture and Technology (TUAT) |
| 3rd Author's Name | Hironori Nakajo |
| 3rd Author's Affiliation | Tokyo University of Agriculture and Technology (TUAT) |
| Speaker | Author-1 |
| Date Time | 2022-01-25 15:35:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | VLD2021-72, CPSY2021-41, RECONF2021-80 |
| Volume (vol) | vol.121 |
| Number (no) | no.342(VLD), no.343(CPSY), no.344(RECONF) |
| Page | pp.132-137 |
| #Pages | 6 |
| Date of Issue | 2022-01-17 (VLD, CPSY, RECONF) |
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