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Paper Abstract and Keywords
Presentation 2022-03-07 15:30
High-throughput In-Memory Accelerator for Binarized Neural Network based on 8T-SRAM
Hiroto Tagata, Hiromitsu Awano (Kyoto Univ.) VLD2021-88 HWS2021-65
Abstract (in Japanese) (See Japanese page) 
(in English) An in-memory accelerator for binary deep neural networks is presented.
The proposed circuit doubled the execution speed of product-sum operations by using bit-lines independently, which are usually used complementarily.
The proposed circuit achieved 92.47% classification accuracy of MNIST in simulations, and its energy consumption is reduced by 28% from existing research.
Keyword (in Japanese) (See Japanese page) 
(in English) Deep neural network / Binary neural network / In-memory computing / / / / /  
Reference Info. IEICE Tech. Rep., vol. 121, no. 412, VLD2021-88, pp. 63-68, March 2022.
Paper # VLD2021-88 
Date of Issue 2022-02-28 (VLD, HWS) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2021-88 HWS2021-65

Conference Information
Committee VLD HWS  
Conference Date 2022-03-07 - 2022-03-08 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for System-on-Silicon, Hardware Security, etc. 
Paper Information
Registration To VLD 
Conference Code 2022-03-VLD-HWS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) High-throughput In-Memory Accelerator for Binarized Neural Network based on 8T-SRAM 
Sub Title (in English)  
Keyword(1) Deep neural network  
Keyword(2) Binary neural network  
Keyword(3) In-memory computing  
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1st Author's Name Hiroto Tagata  
1st Author's Affiliation Kyoto University (Kyoto Univ.)
2nd Author's Name Hiromitsu Awano  
2nd Author's Affiliation Kyoto University (Kyoto Univ.)
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Speaker Author-1 
Date Time 2022-03-07 15:30:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2021-88, HWS2021-65 
Volume (vol) vol.121 
Number (no) no.412(VLD), no.413(HWS) 
Page pp.63-68 
#Pages 6 
Date of Issue 2022-02-28 (VLD, HWS) 

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