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Paper Abstract and Keywords
Presentation 2022-12-03 15:50
A RISC-V Soft-core Processor with Custom VLIW Extension for Spiking Neural Network Accelerator
Mingyang Li, Yuki Hayashida (Mie Univ.) MBE2022-40 NC2022-62
Abstract (in Japanese) (See Japanese page) 
(in English) We aim to develop an embedded accelerator for spiking neural networks (SNN). In order to develop prototypes of various SNN models, which are still in the process of development, a programmable logic device, Field-Programmable Gate Array (FPGA) is considered effective for high-speed operation. However, implementation of an SNN model using a conventional state machine requires a lot of effort for the operation verification and debugging, and thus would not suitable for the prototype development. Therefore, we designed a soft-core microprocessor based on the RISC-V instruction set architecture, which can be used to implement various SNN models by programing and is independent from a specific hardware platform. In particular, it incorporated a custom-designed structure that enabled execution of up to four instructions in parallel with the Very Long Instruction Word extension. In this paper, we mainly explain its design.
Keyword (in Japanese) (See Japanese page) 
(in English) Spiking Neural Network / RISC-V / Very Long Instruction Word / Field-Programmable Gate Array / / / /  
Reference Info. IEICE Tech. Rep., vol. 122, no. 292, NC2022-62, pp. 86-91, Dec. 2022.
Paper # NC2022-62 
Date of Issue 2022-11-26 (MBE, NC) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF MBE2022-40 NC2022-62

Conference Information
Committee MBE NC  
Conference Date 2022-12-03 - 2022-12-03 
Place (in Japanese) (See Japanese page) 
Place (in English) Osaka Electro-Communication University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) NC, ME, etc. 
Paper Information
Registration To NC 
Conference Code 2022-12-MBE-NC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A RISC-V Soft-core Processor with Custom VLIW Extension for Spiking Neural Network Accelerator 
Sub Title (in English)  
Keyword(1) Spiking Neural Network  
Keyword(2) RISC-V  
Keyword(3) Very Long Instruction Word  
Keyword(4) Field-Programmable Gate Array  
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1st Author's Name Mingyang Li  
1st Author's Affiliation Mie University (Mie Univ.)
2nd Author's Name Yuki Hayashida  
2nd Author's Affiliation Mie University (Mie Univ.)
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Speaker Author-1 
Date Time 2022-12-03 15:50:00 
Presentation Time 25 minutes 
Registration for NC 
Paper # MBE2022-40, NC2022-62 
Volume (vol) vol.122 
Number (no) no.291(MBE), no.292(NC) 
Page pp.86-91 
#Pages 6 
Date of Issue 2022-11-26 (MBE, NC) 

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