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Paper Abstract and Keywords
Presentation 2023-01-23 10:55
Partitioning and Distributing Circuit Using HLS Split Compilation Tool for Reconfigurable Virtual Accelerator (ReVA)
Kazuki Yaguchi, Eriko Maeda, Daichi Teruya (TUAT), Yasunori Osana (Univ. of the Ryukyus), Takefumi Miyoshi (WasaLabo), Hironori Nakajo (TUAT) VLD2022-57 RECONF2022-80
Abstract (in Japanese) (See Japanese page) 
(in English) Currently, hardware acceleration with FPGAs is often used for accelerating computational processes in fields such as artificial intelligence (AI) and high-performance computing (HPC). However, in recent years, these operations have become more enormous and complex, resulting in hardware resource shortages and other problems. To overcome this problem, we have been investigating Reconfigurable Virtual Accelerator (ReVA). In this paper, we describe a prototype of ReVA's circuit distribution, which implements circuits on multiple FPGAs independently of the input design structure by an extension of RapidStream, an open-source HLS automated split compilation tool.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / hardware acceleration / HLS / circuit partitioning / / / /  
Reference Info. IEICE Tech. Rep., vol. 122, no. 354, RECONF2022-80, pp. 7-12, Jan. 2023.
Paper # RECONF2022-80 
Date of Issue 2023-01-16 (VLD, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2022-57 RECONF2022-80

Conference Information
Committee IPSJ-SLDM RECONF VLD  
Conference Date 2023-01-23 - 2023-01-24 
Place (in Japanese) (See Japanese page) 
Place (in English) Raiosha, Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc. 
Paper Information
Registration To RECONF 
Conference Code 2023-01-SLDM-RECONF-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Partitioning and Distributing Circuit Using HLS Split Compilation Tool for Reconfigurable Virtual Accelerator (ReVA) 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) hardware acceleration  
Keyword(3) HLS  
Keyword(4) circuit partitioning  
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1st Author's Name Kazuki Yaguchi  
1st Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
2nd Author's Name Eriko Maeda  
2nd Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
3rd Author's Name Daichi Teruya  
3rd Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
4th Author's Name Yasunori Osana  
4th Author's Affiliation University of the Ryukyus (Univ. of the Ryukyus)
5th Author's Name Takefumi Miyoshi  
5th Author's Affiliation WasaLabo, LLC. (WasaLabo)
6th Author's Name Hironori Nakajo  
6th Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
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Speaker Author-1 
Date Time 2023-01-23 10:55:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2022-57, RECONF2022-80 
Volume (vol) vol.122 
Number (no) no.353(VLD), no.354(RECONF) 
Page pp.7-12 
#Pages 6 
Date of Issue 2023-01-16 (VLD, RECONF) 

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