Paper Abstract and Keywords |
Presentation |
2023-01-23 10:55
Partitioning and Distributing Circuit Using HLS Split Compilation Tool for Reconfigurable Virtual Accelerator (ReVA) Kazuki Yaguchi, Eriko Maeda, Daichi Teruya (TUAT), Yasunori Osana (Univ. of the Ryukyus), Takefumi Miyoshi (WasaLabo), Hironori Nakajo (TUAT) VLD2022-57 RECONF2022-80 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Currently, hardware acceleration with FPGAs is often used for accelerating computational processes in fields such as artificial intelligence (AI) and high-performance computing (HPC). However, in recent years, these operations have become more enormous and complex, resulting in hardware resource shortages and other problems. To overcome this problem, we have been investigating Reconfigurable Virtual Accelerator (ReVA). In this paper, we describe a prototype of ReVA's circuit distribution, which implements circuits on multiple FPGAs independently of the input design structure by an extension of RapidStream, an open-source HLS automated split compilation tool. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
FPGA / hardware acceleration / HLS / circuit partitioning / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 122, no. 354, RECONF2022-80, pp. 7-12, Jan. 2023. |
Paper # |
RECONF2022-80 |
Date of Issue |
2023-01-16 (VLD, RECONF) |
ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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VLD2022-57 RECONF2022-80 |
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