IEICE Technical Committee Submission System
Advance Program
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top  Go Back   / [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 

Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Minako Ikeda (NTT)
Vice Chair Shigetoshi Nakatake (Univ. of Kitakyushu)
Secretary Makoto Miyamura (NBS), Masashi Imai (Hirosaki Univ.)
Assistant Takuma Nishimoto (Hitachi)

Technical Committee on Reconfigurable Systems (RECONF) [schedule] [select]
Chair Kentaro Sano (RIKEN)
Vice Chair Yoshiki Yamaguchi (Tsukuba Univ.), Tomonori Izumi (Ritsumeikan Univ.)
Secretary Yuuki Kobayashi (NEC), Yukinori Sato (Toyohashi Univ. of Tech.)
Assistant Yukitaka Takemura (INTEL), Yasunori Osana (Ryukyu Univ.)

Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [schedule] [select]
Chair Hiroyuki Ochi (Ritsumeikan Univ.)
Secretary Kazushi Kawamura (Tokyo Inst. of Tech.), Takashi Imagawa (Meiji Univ.), Hiroki Hosoda (Sony Semiconductor Solutions), Yuki Tanaka (HITACHI)

Conference Date Mon, Jan 23, 2023 10:30 - 16:50
Tue, Jan 24, 2023 10:30 - 15:10
Topics FPGA Applications, etc. 
Conference Place 2F, Raiosha, Hiyoshi Campus, Keio University 
Transportation Guide
Announcement Please make registration in advance (3 days before the workshop). Registration is NOT possible on-site.
If you a student and you do not need proceedings, you can join the workshop without fee (both on-site and online). Please register using the URL below in advance (3 days before the workshop):
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Registration Fee This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on RECONF, VLD.

Mon, Jan 23 AM 
10:30 - 12:10
10:30-10:55 Multi-FPGA design environment using Cyberworkbench, a high-level synthesis tool VLD2022-56 RECONF2022-79 Hiroaki Suzuki (Keio Univ), Wataru Takahashi (NEC), Kazutoshi Wakabayashi (Tokyo Univ), Hideharu Amano (Keio Univ)
10:55-11:20 Partitioning and Distributing Circuit Using HLS Split Compilation Tool for Reconfigurable Virtual Accelerator (ReVA) VLD2022-57 RECONF2022-80 Kazuki Yaguchi, Eriko Maeda, Daichi Teruya (TUAT), Yasunori Osana (Univ. of the Ryukyus), Takefumi Miyoshi (WasaLabo), Hironori Nakajo (TUAT)
11:20-11:45 Initial Evaluation of FPGA Logic Element Placement Method Using Feature Extraction with Autoencoder VLD2022-58 RECONF2022-81 Junpei Sanuki, Ibuki Watanabe, Atsushi Kubota, Tetsuo Hironaka (HCU)
11:45-12:10 Evaluation of reduced routing resources for HPC-Oriented CGRAs VLD2022-59 RECONF2022-82 Carlos Cortes, Boma Adhi, Tomohiro Ueno (RIKEN Center for Computational Science (R-CCS)), Yiyu Tan (Dept of Systems Innovation Engineering Iwate Univ.), Takuya Kojima (Information Science and Technology The Univ. of Tokyo), Artur Podobas (KTH Royal Inst. of Technology), Kentaro Sato (RIKEN Center for Computational Science (R-CCS))
  12:10-13:30 Lunch Break ( 80 min. )
Mon, Jan 23 PM 
13:30 - 14:20
13:30-14:20 [Invited Talk]
Can we say "No FPGA, No Smart City"?
-- Let's declare if we do a smart city, we need FPGAs. --
VLD2022-60 RECONF2022-83
Hiroaki Nishi (Keio Univ.)
  14:20-14:40 Break ( 20 min. )
Mon, Jan 23 PM 
14:40 - 15:55
(6) 14:40-15:05 (IPSJ-SLDM)
(7) 15:05-15:30 (IPSJ-SLDM)
(8) 15:30-15:55 (IPSJ-SLDM)
  15:55-16:10 Break ( 15 min. )
Mon, Jan 23 PM 
16:10 - 16:50
16:10-16:20 VLD2022-61 RECONF2022-84
16:20-16:30 Interface development for Python use of FPGA cluster ESSPER VLD2022-62 RECONF2022-85 Taiki Watanabe (TUT), Kentaro Sano (R-CCS), Yukinori Sato (TUT)
16:30-16:40 A study on optimisation of Back Projection Processing of CT Images using FPGA VLD2022-63 RECONF2022-86 Jumpei Mano, Takaaki Miyajima (Meiji Univ), Peng Chen (AIST), Mohamed Wahib, Kentaro Sano (RIKEN)
16:40-16:50 VLD2022-64 RECONF2022-87
  16:50-17:10 RECONF Award Ceremony ( 20 min. )
Tue, Jan 24 AM 
10:30 - 12:10
10:30-10:55 Measurement results of soft error tolerance of LPDDR4 SDRAM and GDDR5 SDRAM VLD2022-65 RECONF2022-88 Motoki Kamibayashi, Kazutoshi Kobayashi (Kyoto Inst. of Tech.), Masanori Hashimoto (Kyoto Univ.)
10:55-11:20 Study on Wireless Transmission Data Reduction Method and Its Implementation in Emotion Recognition System Using Electroencephalogram VLD2022-66 RECONF2022-89 Yuuki Harada, Daisuke Kanemoto, Tetsuya Hirose (Osaka Univ.)
11:20-11:45 Multi-Droplet Routing based on a Shape-Dependent Velocity Model on MEDA Biochips VLD2022-67 RECONF2022-90 Chiharu Shiro (Ritsumeiakn Univ.), Hiroki Nishikawa (Osaka Univ.), Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita (Ritsumeiakn Univ.)
11:45-12:10 Efficient FPGA Implementation of Binarized Neural Networks Based on Generalized Parallel Counter Tree VLD2022-68 RECONF2022-91 Takahiro Tanigawa, Mugi Noda, Nagisa Ishiura (Kwansei Gakuin Univ.)
  12:10-13:30 Lunch Break ( 80 min. )
Tue, Jan 24 PM 
13:30 - 15:10
13:30-13:55 Implementing a quantum computer simulator Qulacs on FPGAs VLD2022-72 RECONF2022-95 Hideharu Amano, Wei Kaijie (Keio Univ.), Takefumi Miyoshi (Wasalab.), Yoshiki Yamaguchi, Ryohei Niwase (U.niv. of Tsukuba)
13:55-14:20 An Implementation of Generic IP-cores for Linux by Using VIRTIO Interface VLD2022-70 RECONF2022-93 Kota Asanuma (TUAT/e-trees), Takefumi Miyoshi (e-trees)
14:20-14:45 Leveraging dynamic parameter for solution search acceleration in bio-inspired hardware SAT solver VLD2022-71 RECONF2022-94 Anh Hoang Ngoc Nguyen (Fujitsu ltd.)
14:45-15:10 VLD2022-69 RECONF2022-92 Akinobu Tomori (Univ. Ryukyu), Yasunori Osana (Univ. Ryukyus)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Masashi IMAI (Hirosaki Univ. )
E--mail: bi-u 
Announcement See also VLD's homepage:
RECONF Technical Committee on Reconfigurable Systems (RECONF)   [Latest Schedule]
Contact Address Chair: Kentaro Sano (RIKEN) 
Announcement RECONF website
RECONF slack
IPSJ-SLDM Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)   [Latest Schedule]
Contact Address Kazushi Kawamura (Tokyo Inst. of Tech.)
E--mail: arciir 
Announcement Please see the IPSJ-SLDM page below:

Last modified: 2023-01-22 20:14:37

Notification: Mail addresses are partially hidden against SPAM.

[Download Paper's Information (in Japanese)] <-- Press download button after click here.
[Cover and Index of IEICE Technical Report by Issue]

[Presentation and Participation FAQ] (in Japanese)

[Return to VLD Schedule Page]   /   [Return to RECONF Schedule Page]   /   [Return to IPSJ-SLDM Schedule Page]   /  
 Go Top  Go Back   / [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 

[Return to Top Page]

[Return to IEICE Web Page]

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan