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Paper Abstract and Keywords
Presentation 2023-01-24 11:45
Efficient FPGA Implementation of Binarized Neural Networks Based on Generalized Parallel Counter Tree
Takahiro Tanigawa, Mugi Noda, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2022-68 RECONF2022-91
Abstract (in Japanese) (See Japanese page) 
(in English) Binarized neural networks (BNN) allow compact hardware implementation by binarizing weight values and neuron activations.

The critical path delay of a combinational circuit implementing a BNN neuron may be curbed by adopting a Wallace tree of full-adders.

However, in FPGA implementation, a 3-input full-adder does not make full use of LUTs of more than 5 inputs.

This paper proposes the use of a GPC (generalized parallel counter) based compressor tree in FPGA implementation of a BNN neuron to reduce both the delay and size of the resulting circuit.

We further enhance the efficiency of the circuit by reducing the comparison of the popcount and threshould into reference to the carry signal from the compressor tree.

The critical path delay and the slice count of our BNN neuron, implemented on a Xilinx Artinx-7 FPGA, were smaller by 8.9% and 6.3%, respectively, compared to those of the circuit produced by simple
logic synthesis, at number of inputs 256.
Keyword (in Japanese) (See Japanese page) 
(in English) binarized neural network / BNN / generalized parallel counter / FPGA / compressor tree / / /  
Reference Info. IEICE Tech. Rep., vol. 122, no. 353, VLD2022-68, pp. 50-55, Jan. 2023.
Paper # VLD2022-68 
Date of Issue 2023-01-16 (VLD, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2022-68 RECONF2022-91

Conference Information
Committee IPSJ-SLDM RECONF VLD  
Conference Date 2023-01-23 - 2023-01-24 
Place (in Japanese) (See Japanese page) 
Place (in English) Raiosha, Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc. 
Paper Information
Registration To VLD 
Conference Code 2023-01-SLDM-RECONF-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Efficient FPGA Implementation of Binarized Neural Networks Based on Generalized Parallel Counter Tree 
Sub Title (in English)  
Keyword(1) binarized neural network  
Keyword(2) BNN  
Keyword(3) generalized parallel counter  
Keyword(4) FPGA  
Keyword(5) compressor tree  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Takahiro Tanigawa  
1st Author's Affiliation Kwansei Gakuin University (Kwansei Gakuin Univ.)
2nd Author's Name Mugi Noda  
2nd Author's Affiliation Kwansei Gakuin University (Kwansei Gakuin Univ.)
3rd Author's Name Nagisa Ishiura  
3rd Author's Affiliation Kwansei Gakuin University (Kwansei Gakuin Univ.)
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Speaker Author-1 
Date Time 2023-01-24 11:45:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2022-68, RECONF2022-91 
Volume (vol) vol.122 
Number (no) no.353(VLD), no.354(RECONF) 
Page pp.50-55 
#Pages 6 
Date of Issue 2023-01-16 (VLD, RECONF) 

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