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Paper Abstract and Keywords
Presentation 2023-02-28 15:15
A Seed Generation Method for Multiple Random Pattern Resistant Transition Faults for BIST
Yangling Xu, Rei Miura, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (KSU) DC2022-89
Abstract (in Japanese) (See Japanese page) 
(in English) With shrinking feature sizes, growing clock frequencies, and decreasing power supply voltage, modern very large integrated circuits are increasingly suffering from the impact of timing related defects. Therefore, testing for transition faults is necessary. It is important to reduce test cost and improve test quality to deal with the complexity of fault models. To resolve this problem, built-in self-test (BIST) technique is widely used. However, since BIST uses pseudo-random pattern testing, fault coverage is not high due to the existence of random pattern resistant faults. Therefore, in BIST, reseed techniques have been proposed and one-pass seed generation methods which deal with the model combined the functions of the circuit under test and the pseudo-random pattern generator. In this paper, to reduce the number of seeds we use a pseudo-Boolean optimization (PBO) to generate seeds for multiple target faults and PBO maximizes the number of detected target faults. Furthermore, to ensure that the test patterns applied from the generated seed are capture-safe, we propose a one-pass seed generation method for multiple target faults with a power consumption threshold constraint using PBO.
Keyword (in Japanese) (See Japanese page) 
(in English) BIST / transition faults / seed generation / Pseudo-Boolean optimization / low power consumption / / /  
Reference Info. IEICE Tech. Rep., vol. 122, no. 393, DC2022-89, pp. 39-44, Feb. 2023.
Paper # DC2022-89 
Date of Issue 2023-02-21 (DC) 
ISSN Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2023-02-28 - 2023-02-28 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To DC 
Conference Code 2023-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Seed Generation Method for Multiple Random Pattern Resistant Transition Faults for BIST 
Sub Title (in English)  
Keyword(1) BIST  
Keyword(2) transition faults  
Keyword(3) seed generation  
Keyword(4) Pseudo-Boolean optimization  
Keyword(5) low power consumption  
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1st Author's Name Yangling Xu  
1st Author's Affiliation Nihon university (Nihon Univ)
2nd Author's Name Rei Miura  
2nd Author's Affiliation Nihon university (Nihon Univ)
3rd Author's Name Toshinori Hosokawa  
3rd Author's Affiliation Nihon university (Nihon Univ)
4th Author's Name Masayoshi Yoshimura  
4th Author's Affiliation Kyoto Sangyo University (KSU)
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Speaker Author-3 
Date Time 2023-02-28 15:15:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2022-89 
Volume (vol) vol.122 
Number (no) no.393 
Page pp.39-44 
#Pages
Date of Issue 2023-02-21 (DC) 


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