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| Presentation | 2023-07-06 10:10 Performance Improvement by Memory access and Process-level Pipelining for High-level Synthesized Sprite Drawing Hardware Yuka Otani, Akira Yamawaki (Kyutech)  CAS2023-3 VLD2023-3 SIP2023-19 MSS2023-3 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | A mobile terminal with hardware reconfigurability can achieve higher performance and lower power consumption by performing the high computational task as a hardware module. This paper develops an optimized software of 2D sprite drawing for high-level synthesis, HLS, to realize a game application on the proposed mobile terminal. The HLS can convert automatically from software to hardware module. A software description method is proposed to make the HLS generate a well-organized hardware module. Our proposal loads the sprite and background images simultaneously from the memory while compositing them. Then, the composited results are stored into the memory. In addition, the former and latter processes are overlapped. Experimental results measured on a real machine show that our high-level synthesized hardware can achieve a performance improvement of 1.6 times and a power efficiency of 16 times compared with a software execution. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | High-Level Synthesis (HLS) / Sprite / Drawing / Game library / FPGA / Software / Hardware / | |
| Reference Info. | IEICE Tech. Rep., vol. 123, no. 97, CAS2023-3, pp. 10-15, July 2023. | |
| Paper # | CAS2023-3 | |
| Date of Issue | 2023-06-29 (CAS, VLD, SIP, MSS) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CAS2023-3 VLD2023-3 SIP2023-19 MSS2023-3 |
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| Conference Information | |
| Committee | MSS CAS SIP VLD |
| Conference Date | 2023-07-06 - 2023-07-07 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | CAS |
| Conference Code | 2023-07-MSS-CAS-SIP-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Performance Improvement by Memory access and Process-level Pipelining for High-level Synthesized Sprite Drawing Hardware |
| Sub Title (in English) | |
| Keyword(1) | High-Level Synthesis (HLS) |
| Keyword(2) | Sprite |
| Keyword(3) | Drawing |
| Keyword(4) | Game library |
| Keyword(5) | FPGA |
| Keyword(6) | Software |
| Keyword(7) | Hardware |
| Keyword(8) | |
| 1st Author's Name | Yuka Otani |
| 1st Author's Affiliation | Kyushu Institute of Technology (Kyutech) |
| 2nd Author's Name | Akira Yamawaki |
| 2nd Author's Affiliation | Kyushu Institute of Technology (Kyutech) |
| 3rd Author's Name | |
| 3rd Author's Affiliation | () |
| 4th Author's Name | |
| 4th Author's Affiliation | () |
| 5th Author's Name | |
| 5th Author's Affiliation | () |
| 6th Author's Name | |
| 6th Author's Affiliation | () |
| Speaker | Author-1 |
| Date Time | 2023-07-06 10:10:00 |
| Presentation Time | 20 minutes |
| Registration for | CAS |
| Paper # | CAS2023-3, VLD2023-3, SIP2023-19, MSS2023-3 |
| Volume (vol) | vol.123 |
| Number (no) | no.97(CAS), no.98(VLD), no.99(SIP), no.100(MSS) |
| Page | pp.10-15 |
| #Pages | 6 |
| Date of Issue | 2023-06-29 (CAS, VLD, SIP, MSS) |
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