| Paper Abstract and Keywords |
| Presentation |
2024-02-28 10:55
System design using DICE-based edge-triggered soft-error-tolerant D-FF Kazuteru Namba (Chiba Univ.) DC2023-95 |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
The recent miniaturization of VLSI has made the effects of
radiation-induced soft errors more serious.
From this, many soft-error tolerant flip-flops have been presented.
The authors presented an edge-triggered soft-error tolerant flip-flop
using an asynchronous RS latch based on a DICE (Dual Interlocked Storage Cell)
as one of them in past work.
This paper has given experimental results to verify its usefulness.
The experimentation built a library using 45 nm technology and then
synthesized ISCAS 89 benchmark circuit with the Design compiler.
Then, the results gave evidence about the usefulness of the edge-triggered FF.
For example, it reduced the area by 4.2% for s838.1 and the clock period of 0.43 ns. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
soft error / DICE (Dual Interlocked Storage Cell) / edge triggered D-flip flop / / / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 123, no. 389, DC2023-95, pp. 7-10, Feb. 2024. |
| Paper # |
DC2023-95 |
| Date of Issue |
2024-02-21 (DC) |
| ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
| Download PDF |
DC2023-95 |
| Conference Information |
| Committee |
DC |
| Conference Date |
2024-02-28 - 2024-02-28 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
|
| Paper Information |
| Registration To |
DC |
| Conference Code |
2024-02-DC |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
System design using DICE-based edge-triggered soft-error-tolerant D-FF |
| Sub Title (in English) |
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| Keyword(1) |
soft error |
| Keyword(2) |
DICE (Dual Interlocked Storage Cell) |
| Keyword(3) |
edge triggered D-flip flop |
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| 1st Author's Name |
Kazuteru Namba |
| 1st Author's Affiliation |
Chiba University (Chiba Univ.) |
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| Speaker |
Author-1 |
| Date Time |
2024-02-28 10:55:00 |
| Presentation Time |
25 minutes |
| Registration for |
DC |
| Paper # |
DC2023-95 |
| Volume (vol) |
vol.123 |
| Number (no) |
no.389 |
| Page |
pp.7-10 |
| #Pages |
4 |
| Date of Issue |
2024-02-21 (DC) |