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| Paper Abstract and Keywords | ||
| Presentation | 2024-02-28 15:05 Locating High Power Consuming Area by Branch and Reconvergence Topology Analysis for Logic Circuit Tomoya Yamashita, Kohei Miyase, Xiaoqing Wen (Kyutech)  DC2023-101 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In recent years, there has been remarkable progress in the manufacturing technology of LSIs (Large Scale Integration). During the development of LSIs, performance has historically been prioritized over power consumption reduction. However, with the widespread use of portable devices, the low power consumption of LSIs has become essential. To achieve low power consumption in LSIs, it is necessary to identify the factors contributing to high power consumption and locate high power consumption areas. Especially during testing, power consumption becomes high. Excessive power consumption caused excessive IR-drop resulting in test malfunction. While recent studies have made progress in identifying high power consumption areas based on the types of logic gates within the circuit, these researches focus on signal value transitions as a factor affecting power consumption. It is hypothesized that signal value transitions occurring at gates involved in branch and reconvergence, and the identification of such gates is crucial for investigating their relationship with power consumption. The signal transition probabilities commonly used in power consumption analysis become inaccurate when branch and reconvergences are included in the circuit, leading to the need for a more detailed investigation for power analysis. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Branch and reconvergence / test power / IR-drop / test malfunction / probability of switching activity / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 123, no. 389, DC2023-101, pp. 41-46, Feb. 2024. | |
| Paper # | DC2023-101 | |
| Date of Issue | 2024-02-21 (DC) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | DC2023-101 |
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| Conference Information | |
| Committee | DC |
| Conference Date | 2024-02-28 - 2024-02-28 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2024-02-DC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Locating High Power Consuming Area by Branch and Reconvergence Topology Analysis for Logic Circuit |
| Sub Title (in English) | |
| Keyword(1) | Branch and reconvergence |
| Keyword(2) | test power |
| Keyword(3) | IR-drop |
| Keyword(4) | test malfunction |
| Keyword(5) | probability of switching activity |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Tomoya Yamashita |
| 1st Author's Affiliation | Kyushu Institute of Technology (Kyutech) |
| 2nd Author's Name | Kohei Miyase |
| 2nd Author's Affiliation | Kyushu Institute of Technology (Kyutech) |
| 3rd Author's Name | Xiaoqing Wen |
| 3rd Author's Affiliation | Kyushu Institute of Technology (Kyutech) |
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| Speaker | Author-1 |
| Date Time | 2024-02-28 15:05:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | DC2023-101 |
| Volume (vol) | vol.123 |
| Number (no) | no.389 |
| Page | pp.41-46 |
| #Pages | 6 |
| Date of Issue | 2024-02-21 (DC) |
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