| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
Technical Committee on Computer Systems (CPSY) (Searched in: 2020)
Search Results: Keywords 'from:2021-01-25 to:2021-01-25'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-25 09:00 |
Online | Online |  VLD2020-39 CPSY2020-22 RECONF2020-58 |
(To be available after the conference date) [more] | VLD2020-39 CPSY2020-22 RECONF2020-58 pp.1-6 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-25 09:25 |
Online | Online | VLD2020-40 CPSY2020-23 RECONF2020-59 |
[more] | VLD2020-40 CPSY2020-23 RECONF2020-59 pp.7-12 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-25 09:50 |
Online | Online | Study on Design and Evaluation of Stream Processing Hardware for Sound Simulation by FDTD method Hiroki Tada (JAIST), Tomohiro Ueno, Atsushi Koshiba, Kentaro Sano (R-CCS), Ryuta Kawano, Yasushi Inoguchi (JAIST) VLD2020-41 CPSY2020-24 RECONF2020-60 |
(To be available after the conference date) [more] | VLD2020-41 CPSY2020-24 RECONF2020-60 pp.13-18 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-25 10:15 |
Online | Online | An implementation and evaluation of Fast Fourier Transform on FPGA for High-performance Computing Takaaki Miyajima, Tomohiro Ueno, Kentaro Sano (RIKEN) VLD2020-42 CPSY2020-25 RECONF2020-61 |
[more] | VLD2020-42 CPSY2020-25 RECONF2020-61 pp.19-24 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-25 10:55 |
Online | Online | [Invited Talk]
System Architecture and Interconnect Development for the Supercomputer "K" and "Fugaku" Yuichiro Ajima (Fujitsu) VLD2020-43 CPSY2020-26 RECONF2020-62 |
This talk introduces how the system architecture and interconnects of the K computer and the supercomputer Fugaku were s... [more] | VLD2020-43 CPSY2020-26 RECONF2020-62 pp.25-30 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-25 12:55 |
Online | Online | VLD2020-44 CPSY2020-27 RECONF2020-63 |
(To be available after the conference date) [more] | VLD2020-44 CPSY2020-27 RECONF2020-63 pp.31-34 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-25 13:20 |
Online | Online | VLD2020-45 CPSY2020-28 RECONF2020-64 |
(To be available after the conference date) [more] | VLD2020-45 CPSY2020-28 RECONF2020-64 pp.35-39 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-25 13:45 |
Online | Online | Throughput improvement of Responsive Link with High Speed Transceiver in FPGA Masahiko Takahashi, Yamasaki Nobuyuki (Keio Univ.) VLD2020-46 CPSY2020-29 RECONF2020-65 |
In a real-time system, there is a requirement that not only the accuracy of the processing result but also the execution... [more] | VLD2020-46 CPSY2020-29 RECONF2020-65 pp.40-45 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-25 14:25 |
Online | Online | Evaluations of FPGA-based Neural Networks using of ODE Hirohisa Watanabe, Hiroki Matsutani (Keio Univ.) VLD2020-47 CPSY2020-30 RECONF2020-66 |
[more] | VLD2020-47 CPSY2020-30 RECONF2020-66 pp.46-51 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-25 14:50 |
Online | Online | Efficient Attention Mechanism by Softmax Function with Trained Coefficient Kaito Hirota (UT), O'uchi Shinichi (AIST), Fujita Masahiro (UT) VLD2020-48 CPSY2020-31 RECONF2020-67 |
BERT is a neural network model which has accomplished state-of-the-art performance on eleven natural language processing... [more] | VLD2020-48 CPSY2020-31 RECONF2020-67 pp.52-57 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-25 15:15 |
Online | Online | A High-speed Convolutional Neural Network Accelerator for an Adaptive Resolution on an FPGA Koki Sayama, Akira Jinguji, Naoto Soga, Hiroki Nakahara (Tokyo Tech) VLD2020-49 CPSY2020-32 RECONF2020-68 |
In recent years, CNN has been used for various tasks in the field of computer vision and has achievedexcellent performan... [more] | VLD2020-49 CPSY2020-32 RECONF2020-68 pp.58-62 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-25 15:40 |
Online | Online | Implementation of Quantized Deep Neural Network on FPGA Pan Hongyi (AIST/The Univ. of Tokyo), Ben Ahmed Akram, Ikegami Tsutomu (AIST), Tominaga Kazuki (The Univ. of Tokyo), Kudoh Tomohiro (AIST/The Univ. of Tokyo) VLD2020-50 CPSY2020-33 RECONF2020-69 |
[more] | VLD2020-50 CPSY2020-33 RECONF2020-69 pp.63-68 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-25 16:20 |
Online | Online | Residual signed-digit number - residual binary number conversion algorithm Yuki Saba, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2020-51 CPSY2020-34 RECONF2020-70 |
By applying SD(Signed-Digit) number representation, redundant residue number representation including negative number ca... [more] | VLD2020-51 CPSY2020-34 RECONF2020-70 pp.69-74 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-25 16:45 |
Online | Online | Comparison of ICA Algorithms in the Compressed Sensing EEG Measurement Framework Using OD-ICA Wataru Okumura, Daisuke Kanemoto, Osamu Maida, Tetsuya Hirose (Osaka Univ) VLD2020-52 CPSY2020-35 RECONF2020-71 |
Compressed sensing gives reduction of power consumption for electroencephalogram (EEG) measurement system. However, ocul... [more] | VLD2020-52 CPSY2020-35 RECONF2020-71 pp.75-79 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-25 17:10 |
Online | Online | Low Power EEG Measurement Using Compressed Sensing Consideration of the Sampling Interval Yuki Okabe, Daisuke Kanemoto (Osaka Univ.), Tomoya Mochizuki (Yamanashi Univ.), Osamu Maida, Tetsuya Hirose (Osaka Univ.) VLD2020-53 CPSY2020-36 RECONF2020-72 |
In recent years, wireless EEG measurement devices that cause less discomfort to the subject have attracted much attentio... [more] | VLD2020-53 CPSY2020-36 RECONF2020-72 pp.80-84 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-25 17:35 |
Online | Online | High speed architectures of decimal counters Shuhei Yanagawa, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2020-54 CPSY2020-37 RECONF2020-73 |
In this study, we propose new architectures for high speed decimal counters. The two kinds of counters are designed usin... [more] | VLD2020-54 CPSY2020-37 RECONF2020-73 pp.85-89 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-26 09:00 |
Online | Online | Acceleration of Database Query Processing Using FPGA Hirohiko Ozaku (UEC), Masato Yoshimi (TIS), Celimuge Wu, Tsutomu Yoshinaga (UEC) VLD2020-55 CPSY2020-38 RECONF2020-74 |
A bottleneck of Big data analysis is a time to transfer large amount of data to the main memory from the storage. The da... [more] | VLD2020-55 CPSY2020-38 RECONF2020-74 pp.90-95 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-26 09:25 |
Online | Online | FPGA Accelerator Design for Real-Time Object Detection Koichiro Ban, Masanori Furuta, Daisuke Kobayashi (Toshiba) VLD2020-56 CPSY2020-39 RECONF2020-75 |
This paper presents a FPGA accelerator design for a real-time object detection algorithm using MASSD (Multi-Scale Attent... [more] | VLD2020-56 CPSY2020-39 RECONF2020-75 pp.96-100 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-26 09:50 |
Online | Online | FPGA Implementation of Semantic Segmentation on LWIR Images for Autonomous Robot Yuichiro Niwa (ATLA), Taiki Fujii (eSOL) VLD2020-57 CPSY2020-40 RECONF2020-76 |
Recently, deep learning of images has made remarkable progress, and its results are being applied to the automatic reco... [more] |
VLD2020-57 CPSY2020-40 RECONF2020-76 pp.101-106 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-26 10:30 |
Online | Online | VLD2020-58 CPSY2020-41 RECONF2020-77 |
(To be available after the conference date) [more] | VLD2020-58 CPSY2020-41 RECONF2020-77 pp.107-112 |
[Return to Top Page]