|
|
| Chair |
|
Tomohiro Yoneda (NII) |
| Vice Chair |
|
Seiji Kajihara (Kyushu Inst. of Tech.) |
| Secretary |
|
Masato Kitagami (Chiba Univ.), Tomohiro Nakamura (Hitachi) |
|
| Conference Date |
Mon, Feb 13, 2012 10:00 - 16:45 |
| Topics |
|
| Conference Place |
|
Copyright
and
reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Mon, Feb 13 AM
10:00 - 10:50 |
| (1) |
10:00-10:25 |
Design of Dual Edge Triggered Flip-Flops and Application to Signal Delay Detection  DC2011-76 |
Yoshihiro Ohkawa, Yukiya Miura (TMU) |
| (2) |
10:25-10:50 |
An Evaluation of the Effects for Hardware Trojan Designs in AES Encryption Circuits DC2011-77 |
Amy Ogita, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.) |
| |
10:50-11:05 |
Break ( 15 min. ) |
Mon, Feb 13 AM
11:05 - 12:20 |
| (3) |
11:05-11:30 |
Pattern Merging for Additional Path Delay Fault Detection with Transition Delay Fault Test DC2011-78 |
Hiroaki Tanaka, Kohei Miyase, Kazunari Enokimoto, Xiaoqing Wen, Seiji Kajihara (Kyutech) |
| (4) |
11:30-11:55 |
Note on Layout-Aware High Accuracy Estimation of Fault Coverage DC2011-79 |
Masayuki Arai, Yoshihiro Shimizu, Kazuhiko Iwasaki (Tokyo Metro. Univ.) |
| (5) |
11:55-12:20 |
A method to reduce shift-toggle rate for low power BIST DC2011-80 |
Takaaki Kato, Senling Wang, Kohei Miyase, Yasuo Sato, Seiji Kajihara (KIT) |
| |
12:20-14:00 |
Lunch Break ( 100 min. ) |
Mon, Feb 13 PM
14:00 - 15:15 |
| (6) |
14:00-14:25 |
A new problem at Boundary-Scan testing
-- an internal disruption within IC during interconnect testing -- DC2011-81 |
Shuichi Kameyama (Fujitsu & Ehime Univ.), Masayuki Baba (Fujitsu), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) |
| (7) |
14:25-14:50 |
A method to reduce the number of test patterns for transition faults using control point insertions DC2011-82 |
Akihiko Takahashi, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ) |
| (8) |
14:50-15:15 |
A Test Generation Method for Synchronously Designed QDI Circuits DC2011-83 |
Koki Uchida, Eri Murata (NAIST), Satoshi Ohtake (Oita Univ.), Yasuhiko Nakashima (NAIST) |
| |
15:15-15:30 |
Break ( 15 min. ) |
Mon, Feb 13 PM
15:30 - 16:45 |
| (9) |
15:30-15:55 |
An approach for adaptive determination of IDDQ testing criteria based on process parameter estimation DC2011-84 |
Michihiro Shintani, Takashi Sato (Kyoto Univ.) |
| (10) |
15:55-16:20 |
Dynamic Test Scheduling for In-Field Aging Detection DC2011-85 |
Yosuke Morinaga, Tomokazu Yoneda (NAIST), Hyunbean Yi (Hanbat National Univ.), Michiko Inoue (NAIST) |
| (11) |
16:20-16:45 |
Evaluation of a thermal and voltage estimation circuit for field test DC2011-86 |
Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Kohei Miyase (Kyutech), Yukiya Miura (TMU) |
| Announcement for Speakers |
| General Talk | Each speech will have 20 minutes for presentation and 5 minutes for discussion. |
| Contact Address and Latest Schedule Information |
| DC |
Technical Committee on Dependable Computing (DC) [Latest Schedule]
|
| Contact Address |
Masato Kitakami
Graduate School of Advanced Integration Science,
Chiba University
1-33 Yayoi-cho Inage-ku, Chiba 263-8522 JAPAN
TEL/FAX +43.290.3039
E- :    f ulty  ba-u |
Last modified: 2011-12-15 15:29:59
|