|
|
| Chair |
|
Shinji Kimura |
| Vice Chair |
|
Hirofumi Hamamura |
| Secretary |
|
Yusuke Matsunaga, Toshiyuki Shibuya |
|
| Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) |
[schedule] [select]
|
|
| Chair |
|
Takashi Kambe |
| Secretary |
|
Masato Edahiro, Mitsuhisa Ohnishi, Kiyoharu Hamaguchi |
|
| Conference Date |
Thu, May 11, 2006 14:00 - 17:00
Fri, May 12, 2006 09:00 - 14:30 |
| Topics |
|
| Conference Place |
Ehime University |
Contact
Person |
Prof. Hiroshi Takahashi
089-927-9957 |
Thu, May 11 PM
14:00 - 16:00 |
| (1) |
14:00-14:30 |
Online FPGA Placement Using I/O Routing Information |
Mitsuru Tomono, Masaki Nakanishi, Shigeru Yamashita (NAIST), Kazuo Nakajima (Univ. of Maryland), Katsumasa Watanabe (NAIST) |
| (2) |
14:30-15:00 |
Dynamic Reconfigurable Wiring Architecture and Its Application to Hardware Mapping |
Shinji Kimura (Waseda Univ.) |
| (3) |
15:00-15:30 |
A Software-level Energy Reduction Technique for Embedded Microprocessor Exploiting Narrow Bitwidth Operations |
Seiichiro Yamaguchi, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) |
| (4) |
15:30-16:00 |
Automatic Generation of Custom Instructions with Memory Access and Resource Sharing |
Kenshu Seto, Masahiro Fujita (Univ. of Tokyo) |
Thu, May 11 PM
16:15 - 17:00 |
| (5) |
16:15-17:00 |
[Invited Talk]
Configurable Processor Design Environment ASIP Meister |
Masaharu Imai, Ittetsu Taniguchi, Yoshinori Takeuchi, Keishi Sakanushi (Osaka Univ.) |
Fri, May 12 AM
09:00 - 10:30 |
| (6) |
09:00-09:30 |
Bottom-up Equivalence Checking for SpecC Programs |
Subash Shankar (City Univ. of New York), Masahiro Fujita (Univ. of Tokyo) |
| (7) |
09:30-10:00 |
An Approach to Formal Equivalence Checking by Symbolic Simulation between Behavioral and RTL Designs |
Takeshi Matsumoto, Satoshi Komatsu, Masahiro Fujita (Univ. of Tokyo) |
| (8) |
10:00-10:30 |
An Implementation of a Ternary-valued Logic Simulator using a Value-independent Simulator Kernel |
Takatomi Wada, Yasushi Hibino (JAIST) |
Fri, May 12 AM
10:45 - 11:45 |
| (9) |
10:45-11:15 |
Efficient generation method of indirect implication on ATPG |
Masayoshi Yoshimura (FLEETS), Seiji Kajihara (KIT), Yusuke Matsunaga (Kyushu University) |
| (10) |
11:15-11:45 |
Power-Conscious Microprocessor-Based Testing of System-on-Chip |
Fawnizu Azmadi Hussin, Tomokazu Yoneda (NAIST), Alex Orailoglu (Univ. of California), Hideo Fujiwara (NAIST) |
Fri, May 12 PM
13:00 - 14:30 |
| (11) |
13:00-13:30 |
Reduction of Equalizing Circuit Area for 8-VSB Demodulator Using the Result of Correlation Operation |
Kazumi Kawashima, Yusuke Konishi, Yusuke Hashiguchi, Yuu Yamamoto, Masahiro Numa (Kobe Univ.) |
| (12) |
13:30-14:00 |
Delay and Power Consumption of Integer Multipiler
-- Comparison of Wallace and Dadda tree -- |
Masayoshi Tachibana (KUT) |
| (13) |
14:00-14:30 |
Measurement and Analysis of Delay and Power Variations in 90nm CMOS Circuits |
Masaki Yamaguchi (Kyushu Univ.), Yang Yuan (Xi'an Univ. of Technology), Kosuke Tarumi, Ryota Sakamoto, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) |
| Announcement for Speakers |
| General Talk | Each speech will have 25 minutes for presentation and 5 minutes for discussion. |
| Contact Address and Latest Schedule Information |
| VLD |
Technical Committee on VLSI Design Technologies (VLD) [Latest Schedule]
|
| Contact Address |
Yusuke Matsunaga (Kyushu University)
TEL +81-92-583-7621, FAX +81-92-583-1338
E- : matsunaga@ c.csce.kyushu-u.ac.jp |
| Announcement |
You will see the latest information at the below WEB page.
http://www.ieice.org/vld/index.html |
| IPSJ-SLDM |
Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [Latest Schedule]
|
| Contact Address |
|
Last modified: 2006-04-18 12:40:00
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