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| Chair |
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Yuichi Sakurai (Hitachi) |
| Vice Chair |
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Hiroyuki Tomiyama (Ritsumeikan Univ.) |
| Secretary |
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Yukihiro Sasagawa (Socionext), Kenshu Seto (Kumamot Univ.) |
| Assistant |
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Takuma Nishimoto (Hitachi), Ami TANAKA (Rits), Masayuki Odagawa (Cadence Design Systems, Japan) |
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| Chair |
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Yuichi Hayashi (NAIST) |
| Vice Chair |
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Toru Akishita (Sony Semiconductor Solutions), Noriyuki Miura (Osaka Univ.) |
| Secretary |
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Toshihiro Sato (hd Lab,), Junichi Sakamoto (AIST) |
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| Chair |
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Makoto Ikeda (Univ. of Tokyo) |
| Vice Chair |
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Hayato Wakabayashi (Sony Semiconductor Solutions) |
| Secretary |
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Yoshiaki Yoshihara (Kioxia), Jun Shiomi (Osaka Univ.) |
| Assistant |
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Ryo Shirai (Kyoto Univ.), Kyoya Takano (Tokyo Univ. of Sci.), Takeshi Kuboki (Kumamoto University) |
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| Conference Date |
Wed, Mar 5, 2025 14:00 - 17:10
Thu, Mar 6, 2025 09:45 - 20:00
Fri, Mar 7, 2025 09:45 - 16:45
Sat, Mar 8, 2025 09:20 - 12:30
[updated] |
| Topics |
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| Conference Place |
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| Transportation Guide |
https://minnanospace.com/naha-asahimachi-space/ |
| Registration Fee |
This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on HWS, ICD, VLD. |
| Due for Registration |
Please proceed the payment of registration fee by 3 days before the workshop date. The meeting URL will be sent from one of the secretaries of the committee via e-mail, just before the workshop date. |
| Registration for Online |
If you will join the workshop/conference held in online/hybrid style, please make your registration here, for getting the meeting ID and pass code. (Japanese page) |
Wed, Mar 5
14:00 - 15:15 |
| (1) |
14:00-14:25 |
Error Correation Methods with Node Redundancy Considering Node Level in DMFB |
Koki Suzuki, Shigeru Yamashita, Hiroyuki Tomiyama (Ritsumeikan Univ.), Ankur Gupta (NSUT) |
| (2) |
14:25-14:50 |
Speeding Up a Routing Method Considering Droplet Division on MEDA Biochips by Dijkstra's Method |
Issei Nakamura, Shigeru Yamashita, Hiroyuki Tomiyama (Ritsumeikan Univ.), Ankur Gupta (NSUT) |
| (3) |
14:50-15:15 |
A Fast Droplet Routing Algorithm for MEDA-Based DMFB |
Emuun Purevdagva, Masayuki Shimoda, Satoshi Tayu, Atsushi Takahashi (Science Tokyo) |
| |
15:15-15:30 |
Break ( 15 min. ) |
Wed, Mar 5
15:30 - 17:10 |
| (4) |
15:30-15:55 |
A Motif Extraction Method By Subsequence Classification Using Random Forests |
Jigen Murata, Masato Inagi, Martin Lukac, Shin'ichi Wakabayashi, Shinobu Nagayama (HCU) |
| (5) |
15:55-16:20 |
Placement of Items to be Picked for Products in Manufacturing Industries |
Natsumi Nakayama, Masato Inagi, Martin Lukac, Shin'ichi Wakabayashi, Shinobu Nagayama (HCU) |
| (6) |
16:20-16:45 |
A Note on 4-Layer U-shape Bottleneck Channel Routing |
Yo Sakakura, Satoshi Tayu, Masayuki Shimoda, Atsushi Takahashi (Science Tokyo) |
| (7) |
16:45-17:10 |
Analog Primitive Cell Identification for Large-scale Analog Circuit with Graph Neural Network |
Chen Geng, Shigetoshi Nakatake (Univ. of Kitakyushu) |
Thu, Mar 6
09:45 - 11:00 |
| (8) |
09:45-10:10 |
A Study on Data Transfer from Synchronous Circuits to Asynchronous Circuits Using AXI Lite |
Shogo Semba, Hiroshi Saito (UoA) |
| (9) |
10:10-10:35 |
Design and evaluation of image processing architecture based on Network on Chip |
Hayato Miyoshi, Rento Yoshihara, Ryuya Kadota, Kanto Kawakami, Masafumi Kondo (Okayama Science Univ.) |
| (10) |
10:35-11:00 |
Implementation of the Sort Instruction in a RISC-V Processor Using Chipyard |
Daiki Masuda, Yoshinori Takeuchi (Kindai Univ.) |
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11:00-11:15 |
Break ( 15 min. ) |
Thu, Mar 6
11:15 - 12:30 |
| (11) |
11:15-11:40 |
Efficient and Accurate SC Arithmetic Circuits Using Bit Manipulation Based on Interval Partitioning of Bit Strings |
Yota Yanagida, Shigeru Yamashita (Ritsumeikan Univ.) |
| (12) |
11:40-12:05 |
An efficient LSI implementation of popcount for convolution operations in binarized neural networks |
Reiji Kikuchi, Kazuhito Ito (Saitama Univ.) |
| (13) |
12:05-12:30 |
An implementation of convolution and pooling operations in binarized neural networks on register-bridge architecture LSI |
Yuichiro Iwai, Kazuhito Ito (Saitama Univ.) |
| |
12:30-14:00 |
Break ( 90 min. ) |
Thu, Mar 6
14:00 - 15:15 |
| (14) |
14:00-14:25 |
Application of Single-Base RNS Montgomery Multiplication Algorithm |
Shinichi Kawamura (AIST), Yuichi Komano (CIT) |
| (15) |
14:25-14:50 |
Implementation Architecture and Circuit Fabrication for Photonic Circuits of Symmetric Key Cryptography |
Junko Takahashi, Shota Kita, Akihiko Shinya (NTT), Kazumaro Aoki (Bunkyo Univ), Koji Chida (Gunma Univ), Fumitaka Hoshino (Univ. of Nagasaki) |
| (16) |
14:50-15:15 |
Re-evaluation of Tamper-resistant Designs Using a Side-channel Attack Platform for Netlist |
Ryoma Katsube, Tomoaki Ukezono (Fukuoka Univ) |
| |
15:15-15:30 |
Break ( 15 min. ) |
Thu, Mar 6
15:30 - 17:10 |
| (17) |
15:30-15:55 |
[Memorial Lecture]
A Study on SQA Acceleration Using Multi-FPGA for Route Optimization of Large-scale Mobile Robots System |
Thinh NguyenQuang, Kosuke Matsuyama (Tohoku University), Keisuke Shimizu, Hiroki Sugano, Eiji Kurimoto (Sharp Corporation), Hasitha Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Masayuki Ohzeki (Tohoku University) |
| (18) |
15:55-16:20 |
Single-Source Shortest Path FPGA Accelerator Using Multiple Parallel Searches with High-Level Synthesis and Linked List Implementation |
Haopeng Meng, Kazutoshi Wakabayashi, Makoto Ikeda (The University of Tokyo) |
| (19) |
16:20-16:45 |
A Study on Software-Hardware Partitioning Method for SoC FPGAs
[updated] |
Koki Murano, Ryo Yamamoto, Takahiro Morii, Osamu Toyama (Mitsubishi Electric Corp.) |
| (20) |
16:45-17:10 |
A method for mapping and scheduling of operations targeting register-bridge architecture LSIs with memory accesses |
Sota Akashi, Kazuhito Ito (Saitama Univ.) |
Thu, Mar 6 PM Banquet [updated]
18:00 - 20:00 [updated] |
(21)
[updated] |
18:00-20:00
[updated] |
Banquet
[updated] |
Fri, Mar 7
09:45 - 11:00 |
(22)
[updated] |
09:45-10:10 |
N/A |
Ryuta Kawamura, Ryusei Eda, Hibiki Nakanishi, Nozomu Togawa (Waseda Univ.) |
(23)
[updated] |
10:10-10:35 |
N/A |
So Iomori, Ryusei Eda (Waseda Univ.), Ryoichi Kida, Tsuneo Ogasawara (LAC), Nozomu Togawa (Waseda Univ.)
[updated] |
(24)
[updated] |
10:35-11:00 |
Performance Evaluation of Heart Sound Classification Using CNN, BNN, TNN, and SNN |
Reo Taniguchi, Haruto Furuta, Shigetoshi Nakatake (Univ. of Kitakyushu) |
| |
11:00-11:15 |
Break ( 15 min. ) |
Fri, Mar 7
11:15 - 12:30 |
(25)
[updated] |
11:15-11:40 |
MTJ-PUF with Response Reuse and Evaluation of Machine Learning Attack Resistance |
Taiki Tsukada, Kimiyoshi Usami (SIT) |
(26)
[updated] |
11:40-12:05 |
Cost reduction of fine-grained power domain partitioning circuits enabling hardware trojan detection |
Takahiro Ishikawa, Yoshihiro Midoh, Noriyuki Miura (Osaka Univ.), Michihiro Shintani (Kyoto Inst. of Tech.), Jun Shiomi (Osaka Univ.) |
(27)
[updated] |
12:05-12:30 |
Development of Hardware Trojans using Transistor Characteristics in Low Temperatures Environments |
Ayano Takaya, Ryuichi Nakajima (Kyoto Inst. of Tech.), Jun Shiomi (Osaka Univ.), Michihiro Shintani (Kyoto Inst. of Tech.) |
| |
12:30-14:25
[updated] |
Break ( 115 min. )
[updated] |
Fri, Mar 7
14:25 - 15:15 [updated] |
| (28) |
14:25-14:50 |
Study on Application Method of Multiple PLLs for Fault Injection Countermeasures to Cryptographic Modules |
Hikaru Nishiyama (AIST/NAIST), Daisuke Fujimoto, Yuichi Hayashi (NAIST) |
| (29) |
14:50-15:15 |
Pipeline design of LUT-reduction based butterfly unit for high-speed NTT |
Riku Koizumi, Daisuke Fujimoto, Yuichi Hayashi (NAIST) |
| |
15:15-15:30 |
Break ( 15 min. ) |
Fri, Mar 7
15:30 - 16:45 |
| (30) |
15:30-15:55 |
Performance Evaluation of FPGA Evaluation Boards in Cryogenic Environments |
Tomoki Takashima, Akimasa Saito, Masashi Imai (Hirosaki Univ.) |
| (31) |
15:55-16:20 |
Integration of a Quantum Annealing Simulator and a Circuit Simulator and Evaluation of Their Usefulness |
Akimasa Saito, Masashi Imai (Hirosaki Univ.) |
| (32) |
16:20-16:45 |
Miniature Multimodal Olfactory Device with 3D MSS-CMOS Chip Stack |
Naru Kato, Kotaro Naruse, Takuma Matsumori, Jun Shiomi, Yoshihiro Midoh, Tetsuya Hirose (Osaka Univ.), Gaku Imamura (Osaka Univ./NIMS), Genki Yoshikawa (Tsukuba Univ./NIMS), Noriyuki Miura (Osaka Univ.)
[updated] |
Sat, Mar 8
09:20 - 10:35 |
| (33) |
09:20-09:45 |
Interpretable Deep Learning-based Side-channel Analysis Using Kolmogorov-Arnold Networks |
Kota Yoshida (Ritsumeikan Univ.), Sengim Karayalcin (Leiden Univ.), Stjepan Picek (Radboud Univ.) |
| (34) |
09:45-10:10 |
Implementation of Side-channel-attack Environment against In-vehicle ECUs Using CAN Packet Monitoring for Triggering Waveform Acquisition |
Tomoe Kato, Yuta Fukuda, Mizuki Nagahisa, Masato Okuda, Kota Yoshida, Takeshi Fujino (Ritsumeikan Univ.) |
| (35) |
10:10-10:35 |
Optimizing Deep Learning Based Side-Channel Attacks Methods by Preprocessing Based on Autoencoder |
Masaki Morita, Takuya Kojima, Haruto Ishii, Hideki Takase, Hiroshi Nakamura (UTokyo) |
| |
10:35-10:50 |
Break ( 15 min. ) |
Sat, Mar 8
10:50 - 12:30 |
| (36) |
10:50-11:15 |
Hardware-Assisted IoT Security: Real-Time DDoS Detection through Power Side-Channel Analysis |
Qingyu Zeng, Mingyu Yang, Yuko Hara (Science Tokyo) |
| (37) |
11:15-11:40 |
Quantitative Comparison of Fault Attack Vulnerability Detection Tools |
Shoei Nashimoto (Mitsubishi Electric) |
| (38) |
11:40-12:05 |
Hybrid and Hierarchical Detection Flow for Hardware Trojans |
Takafumi Oki, Rikuu Hasegawa, Kazuki Monta, Takuji Miki, Makoto Nagata (Kobe Univ.) |
| (39) |
12:05-12:30 |
Scalability Evaluation of Sensing Security Technology for Surveillance Cameras Using Device Inherence |
Kotaro Naruse, Yoshihiro Midoh, Noriyuki Miura (Osaka Univ.) |
| Announcement for Speakers |
| General Talk | Each speech will have 20 minutes for presentation and 5 minutes for discussion. |
| Contact Address and Latest Schedule Information |
| VLD |
Technical Committee on VLSI Design Technologies (VLD) [Latest Schedule]
|
| Contact Address |
Yukihiro Sasagawa (Socionext) |
| Announcement |
See also VLD's homepage:
http://www.ieice.org/~vld/ |
| HWS |
Technical Committee on Hardware Security (HWS) [Latest Schedule]
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| Contact Address |
Junichi Sakamoto (AIST), Toshihiro Sato (hd Lab, Inc.)
E- :hws- c  |
| ICD |
Technical Committee on Integrated Circuits and Devices (ICD) [Latest Schedule]
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| Contact Address |
Ryo Shirai （Kyoto University）
E-:   ii k  -u |
Last modified: 2025-02-05 17:01:14
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