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| Chair |
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Yuichi Sakurai (Hitachi) |
| Vice Chair |
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Hiroyuki Tomiyama (Ritsumeikan Univ.) |
| Secretary |
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Yukihiro Sasagawa (Socionext), Kenshu Seto (Kumamot Univ.) |
| Assistant |
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Takuma Nishimoto (Hitachi), Ami TANAKA (Rits), Masayuki Odagawa (Cadence Design Systems, Japan) |
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| Chair |
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Yuichi Hayashi (NAIST) |
| Vice Chair |
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Toru Akishita (Sony Semiconductor Solutions), Noriyuki Miura (Osaka Univ.) |
| Secretary |
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Toshihiro Sato (hd Lab,), Junichi Sakamoto (AIST) |
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| Chair |
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Makoto Ikeda (Univ. of Tokyo) |
| Vice Chair |
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Hayato Wakabayashi (Sony Semiconductor Solutions) |
| Secretary |
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Yoshiaki Yoshihara (Kioxia), Jun Shiomi (Osaka Univ.) |
| Assistant |
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Ryo Shirai (Kyoto Univ.), Kyoya Takano (Tokyo Univ. of Sci.), Takeshi Kuboki (Kumamoto University) |
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| Conference Date |
Wed, Mar 5, 2025 14:00 - 17:10
Thu, Mar 6, 2025 09:45 - 20:00
Fri, Mar 7, 2025 09:45 - 16:45
Sat, Mar 8, 2025 09:20 - 12:30 |
| Topics |
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| Conference Place |
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| Transportation Guide |
https://minnanospace.com/naha-asahimachi-space/ |
Copyright
and
reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
| Registration Fee |
This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on HWS, ICD, VLD. |
Wed, Mar 5
14:00 - 15:15 |
| (1) |
14:00-14:25 |
Error Correation Methods with Node Redundancy Considering Node Level in DMFB  VLD2024-103 HWS2024-74 ICD2024-94 |
Koki Suzuki, Shigeru Yamashita, Hiroyuki Tomiyama (Ritsumeikan Univ.), Ankur Gupta (NSUT) |
| (2) |
14:25-14:50 |
Speeding Up a Routing Method Considering Droplet Division on MEDA Biochips by Dijkstra's Method VLD2024-104 HWS2024-75 ICD2024-95 |
Issei Nakamura, Shigeru Yamashita, Hiroyuki Tomiyama (Ritsumeikan Univ.), Ankur Gupta (NSUT) |
| (3) |
14:50-15:15 |
Fast Droplet Routing Algorithm for MEDA-Based DMFB VLD2024-105 HWS2024-76 ICD2024-96 |
Emuun Purevdagva, Masayuki Shimoda, Satoshi Tayu, Atsushi Takahashi (Science Tokyo) |
| |
15:15-15:30 |
Break ( 15 min. ) |
Wed, Mar 5
15:30 - 17:10 |
| (4) |
15:30-15:55 |
A Motif Extraction Method By Subsequence Classification Using Random Forests VLD2024-106 HWS2024-77 ICD2024-97 |
Jigen Murata, Masato Inagi, Martin Lukac, Shin'ichi Wakabayashi, Shinobu Nagayama (HCU) |
| (5) |
15:55-16:20 |
Placement of Items to be Picked for Products in Manufacturing Industries VLD2024-107 HWS2024-78 ICD2024-98 |
Natsumi Nakayama, Masato Inagi, Martin Lukac, Shin'ichi Wakabayashi, Shinobu Nagayama (HCU) |
| (6) |
16:20-16:45 |
A Note on 4-Layer U-shape Bottleneck Channel Routing VLD2024-108 HWS2024-79 ICD2024-99 |
Yo Sakakura, Satoshi Tayu, Masayuki Shimoda, Atsushi Takahashi (Science Tokyo) |
| (7) |
16:45-17:10 |
Analog Primitive Cell Identification for Large-scale Analog Circuit with Graph Neural Network VLD2024-109 HWS2024-80 ICD2024-100 |
Chen Geng, Shigetoshi Nakatake (Univ. of Kitakyushu), Nobuto Ono, Katsuya Nishioka, Shigeya Yamaguchi, Takahiro Hikida, Noriteru Matsubara, Yukichi Todoroki (Jedat) |
Thu, Mar 6
09:45 - 11:00 |
| (8) |
09:45-10:10 |
A Study on Data Transfer from Synchronous Circuits to Asynchronous Circuits Using AXI Lite VLD2024-110 HWS2024-81 ICD2024-101 |
Shogo Semba, Hiroshi Saito (UoA) |
| (9) |
10:10-10:35 |
Design and evaluation of image processing architecture based on Network on Chip VLD2024-111 HWS2024-82 ICD2024-102 |
Hayato Miyoshi, Rento Yoshihara, Ryuya Kadota, Kanto Kawakami, Masafumi Kondo (Okayama Science Univ.) |
| (10) |
10:35-11:00 |
Implementation of the Sort Instruction in a RISC-V Processor Using Chipyard VLD2024-112 HWS2024-83 ICD2024-103 |
Daiki Masuda, Yoshinori Takeuchi (Kindai Univ.) |
| |
11:00-11:15 |
Break ( 15 min. ) |
Thu, Mar 6
11:15 - 12:30 |
| (11) |
11:15-11:40 |
Efficient and Accurate SC Arithmetic Circuits Using Bit Manipulation Based on Interval Partitioning of Bit Strings VLD2024-113 HWS2024-84 ICD2024-104 |
Yota Yanagida, Shigeru Yamashita (Ritsumeikan Univ.) |
| (12) |
11:40-12:05 |
An efficient LSI implementation of popcount for convolution operations in binarized neural networks VLD2024-114 HWS2024-85 ICD2024-105 |
Reiji Kikuchi, Kazuhito Ito (Saitama Univ.) |
| (13) |
12:05-12:30 |
An implementation of convolution and pooling operations in binarized neural networks on register-bridge architecture LSI VLD2024-115 HWS2024-86 ICD2024-106 |
Yuichiro Iwai, Kazuhito Ito (Saitama Univ.) |
| |
12:30-14:00 |
Break ( 90 min. ) |
Thu, Mar 6
14:00 - 15:15 |
| (14) |
14:00-14:25 |
Application of Single-Base RNS Montgomery Multiplication Algorithm VLD2024-116 HWS2024-87 ICD2024-107 |
Shinichi Kawamura (AIST), Yuichi Komano (CIT) |
| (15) |
14:25-14:50 |
Implementation Method and Circuit Fabrication for Photonic Circuits of Symmetric Key Cryptography VLD2024-117 HWS2024-88 ICD2024-108 |
Junko Takahashi, Shota Kita, Akihiko Shinya (NTT), Kazumaro Aoki (Bunkyo Univ), Koji Chida (Gunma Univ), Fumitaka Hoshino (Univ. of Nagasaki) |
| (16) |
14:50-15:15 |
Re-evaluation of Tamper-resistant Designs Using a Side-channel Attack Platform for Netlist VLD2024-118 HWS2024-89 ICD2024-109 |
Ryoma Katsube, Tomoaki Ukezono (Fukuoka Univ) |
| |
15:15-15:30 |
Break ( 15 min. ) |
Thu, Mar 6
15:30 - 17:10 |
| (17) |
15:30-15:55 |
[Memorial Lecture]
A Study on SQA Acceleration Using Multi-FPGA for Route Optimization of Large-scale Mobile Robots System VLD2024-119 HWS2024-90 ICD2024-110 |
Thinh NguyenQuang (Tohoku University), Kosuke Matsuyama, Keisuke Shimizu, Hiroki Sugano, Eiji Kurimoto (Sharp Corporation), Hasitha Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Masayuki Ohzeki (Tohoku University) |
| (18) |
15:55-16:20 |
Single-Source Shortest Path FPGA Accelerator Using Multiple Parallel Searches with High-Level Synthesis and Linked List Implementation VLD2024-120 HWS2024-91 ICD2024-111 |
Haopeng Meng, Kazutoshi Wakabayashi, Makoto Ikeda (The University of Tokyo) |
| (19) |
16:20-16:45 |
A Study on Software-Hardware Partitioning Method for SoC FPGAs VLD2024-121 HWS2024-92 ICD2024-112 |
Koki Murano, Ryo Yamamoto, Takahiro Morii, Osamu Toyama (Mitsubishi Electric Corp.) |
| (20) |
16:45-17:10 |
A method for mapping and scheduling of operations targeting register-bridge architecture LSIs with memory accesses VLD2024-122 HWS2024-93 ICD2024-113 |
Sota Akashi, Kazuhito Ito (Saitama Univ.) |
Thu, Mar 6 PM Banquet
18:00 - 20:00 |
| (21) |
18:00-20:00 |
Banquet |
Fri, Mar 7
09:45 - 11:00 |
| (22) |
09:45-10:10 |
N/A VLD2024-123 HWS2024-94 ICD2024-114 |
Ryuta Kawamura, Ryusei Eda, Hibiki Nakanishi, Nozomu Togawa (Waseda Univ.) |
| (23) |
10:10-10:35 |
N/A VLD2024-124 HWS2024-95 ICD2024-115 |
So Iomori, Ryusei Eda (Waseda Univ.), Ryoichi Kida, Tsuneo Ogasawara (LAC), Nozomu Togawa (Waseda Univ.) |
| (24) |
10:35-11:00 |
Performance Evaluation of Heart Sound Classification Using CNN, BNN, TNN, and SNN VLD2024-125 HWS2024-96 ICD2024-116 |
Reo Taniguchi, Haruto Furuta, Yutaro Yamanaka, Shigetoshi Nakatake (Univ. of Kitakyushu) |
| |
11:00-11:15 |
Break ( 15 min. ) |
Fri, Mar 7
11:15 - 12:30 |
| (25) |
11:15-11:40 |
MTJ-PUF with Response Reuse and Evaluation of Machine Learning Attack Resistance VLD2024-126 HWS2024-97 ICD2024-117 |
Taiki Tsukada, Kimiyoshi Usami (SIT) |
| (26) |
11:40-12:05 |
Cost reduction of fine-grained power domain partitioning circuits enabling hardware trojan detection VLD2024-127 HWS2024-98 ICD2024-118 |
Takahiro Ishikawa, Yoshihiro Midoh, Noriyuki Miura (Osaka Univ.), Michihiro Shintani (Kyoto Inst. of Tech.), Jun Shiomi (Osaka Univ.) |
| (27) |
12:05-12:30 |
Development of Hardware Trojans using Transistor Characteristics in Low Temperature Environments VLD2024-128 HWS2024-99 ICD2024-119 |
Ayano Takaya, Ryuichi Nakajima (Kyoto Inst. of Tech.), Jun Shiomi (Osaka Univ.), Michihiro Shintani (Kyoto Inst. of Tech.) |
| |
12:30-14:25 |
Break ( 115 min. ) |
Fri, Mar 7
14:25 - 15:15 |
| (28) |
14:25-14:50 |
Study on Constitution Method of Multiple PLLs for Fault Injection Countermeasures to Cryptographic Modules VLD2024-129 HWS2024-100 ICD2024-120 |
Hikaru Nishiyama (AIST/NAIST), Daisuke Fujimoto, Yuichi Hayashi (NAIST) |
| (29) |
14:50-15:15 |
Pipeline design of LUT-reduction based butterfly unit for high-speed NTT VLD2024-130 HWS2024-101 ICD2024-121 |
Riku Koizumi, Daisuke Fujimoto, Yuichi Hayashi (NAIST) |
| |
15:15-15:30 |
Break ( 15 min. ) |
Fri, Mar 7
15:30 - 16:45 |
| (30) |
15:30-15:55 |
Performance Evaluation of FPGA Evaluation Boards in Cryogenic Environments VLD2024-131 HWS2024-102 ICD2024-122 |
Tomoki Takashima, Akimasa Saito, Masashi Imai (Hirosaki Univ.) |
| (31) |
15:55-16:20 |
Integration of a Quantum Annealing Simulator and a Circuit Simulator and Evaluation of Their Usefulness VLD2024-132 HWS2024-103 ICD2024-123 |
Akimasa Saito, Masashi Imai (Hirosaki Univ.) |
| (32) |
16:20-16:45 |
Miniature Multimodal Olfactory Device with 3D MSS-CMOS Chip Stack VLD2024-133 HWS2024-104 ICD2024-124 |
Naru Kato, Kotaro Naruse, Takuma Matsumori, Jun Shiomi, Yoshihiro Midoh, Tetsuya Hirose (Osaka Univ.), Gaku Imamura (Osaka Univ./NIMS), Genki Yoshikawa (Tsukuba Univ./NIMS), Noriyuki Miura (Osaka Univ.) |
Sat, Mar 8
09:20 - 10:35 |
| (33) |
09:20-09:45 |
Interpretable Deep Learning-based Side-channel Analysis Using Kolmogorov-Arnold Networks VLD2024-134 HWS2024-105 ICD2024-125 |
Kota Yoshida (Ritsumeikan Univ.), Sengim Karayalcin (Leiden Univ.), Stjepan Picek (Radboud Univ.) |
| (34) |
09:45-10:10 |
Implementation of Side-channel-attack Environment against In-vehicle ECUs Using CAN Packet Monitoring for Triggering Waveform Acquisition VLD2024-135 HWS2024-106 ICD2024-126 |
Tomoe Kato, Yuta Fukuda, Mizuki Nagahisa, Masato Okuda, Kota Yoshida, Takeshi Fujino (Ritsumeikan Univ.) |
| (35) |
10:10-10:35 |
Optimizing Deep Learning Based Side-Channel Attacks Methods by Preprocessing Based on Autoencoder VLD2024-136 HWS2024-107 ICD2024-127 |
Masaki Morita, Takuya Kojima, Haruto Ishii, Hideki Takase, Hiroshi Nakamura (UTokyo) |
| |
10:35-10:50 |
Break ( 15 min. ) |
Sat, Mar 8
10:50 - 12:30 |
| (36) |
10:50-11:15 |
Hardware-Assisted IoT Security: Real-Time DDoS Detection through Power Side-Channel Analysis VLD2024-137 HWS2024-108 ICD2024-128 |
Qingyu Zeng, Mingyu Yang, Yuko Hara (Science Tokyo) |
| (37) |
11:15-11:40 |
Quantitative Comparison of Fault Attack Vulnerability Detection Tools VLD2024-138 HWS2024-109 ICD2024-129 |
Shoei Nashimoto (Mitsubishi Electric) |
| (38) |
11:40-12:05 |
Hybrid and Hierarchical Detection Flow for Hardware Trojans VLD2024-139 HWS2024-110 ICD2024-130 |
Takafumi Oki, Rikuu Hasegawa, Kazuki Monta, Takuji Miki, Makoto Nagata (Kobe Univ.) |
| (39) |
12:05-12:30 |
Scalability Evaluation of Sensing Security Technology for Surveillance Cameras Using Device Inherence VLD2024-140 HWS2024-111 ICD2024-131 |
Kotaro Naruse, Yoshihiro Midoh, Noriyuki Miura (Osaka Univ.) |
| Announcement for Speakers |
| General Talk | Each speech will have 20 minutes for presentation and 5 minutes for discussion. |
| Contact Address and Latest Schedule Information |
| VLD |
Technical Committee on VLSI Design Technologies (VLD) [Latest Schedule]
|
| Contact Address |
Yukihiro Sasagawa (Socionext) |
| Announcement |
See also VLD's homepage:
http://www.ieice.org/~vld/ |
| HWS |
Technical Committee on Hardware Security (HWS) [Latest Schedule]
|
| Contact Address |
Junichi Sakamoto (AIST), Toshihiro Sato (hd Lab, Inc.)
E- :hws- c  |
| ICD |
Technical Committee on Integrated Circuits and Devices (ICD) [Latest Schedule]
|
| Contact Address |
Ryo Shirai （Kyoto University）
E-:   ii k  -u |
Last modified: 2025-03-07 08:40:13
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