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Technical Committee on Computer Systems (CPSY) (Searched in: 2017)
Search Results: Keywords 'from:2017-11-06 to:2017-11-06'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 10:30 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | hCODE 2.0: An Open-source Platform for FPGA Cluster System Hiroki Nakagawa, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)  VLD2017-27 DC2017-33 |
In recent years, major cloud providers such as Amazon and Microsoft are improving cloud applications using FPGAs. By in... [more] |
VLD2017-27 DC2017-33 pp.1-6 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 10:55 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Design Environment Construction for Three-Dimensional Sound Processor using High-Level Synthesis Saya Ohira, Naoki Tsuchiya, Tetsuya Matsumura (Nihon Univ.) VLD2017-28 DC2017-34 |
A three-dimensional (3D) sound processor architecture that includes 3D sound processing intellectual property (IP) cores... [more] | VLD2017-28 DC2017-34 pp.7-12 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 11:20 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Considerations of Inside Structures for Approximate Multipliers Masahiro Inoue, Kaori Tajima, Hiroyuki Baba, Tongxin Yang, Tomoaki Ukezono, Toshinori Sato (Fukuoka Univ.) VLD2017-29 DC2017-35 |
Approximate arithmetic circuits are logic circuits which do not generate accurate arithmetic results.Approximate arithme... [more] | VLD2017-29 DC2017-35 pp.13-18 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 13:00 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | [Invited Talk]
Superconducting quantum computing Yasunobu Nakamura (UTokyo) CPM2017-79 ICD2017-38 IE2017-64 |
[more] | CPM2017-79 ICD2017-38 IE2017-64 p.1 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 13:00 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Optimization of Cryptographic Hardware for Optimal Ate Pairing over BN Curves Tadayuki Ichihashi, Hiromitsu Awano, Makoto Ikeda (Tokyo Univ.) VLD2017-30 DC2017-36 |
[more] | VLD2017-30 DC2017-36 pp.19-24 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 13:25 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Hardware Implementation of Elliptic Curve Cryptography for Sensor-Node Applications Ryosuke Saito, Hiromitsu Awano, Makoto Ikeda (The Univ. of Tokyo) |
[more] | |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 13:50 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | An Evaluation for the Number of Decoding Key for Logic Encryption Methods for IP Cores Hashidate Hidemi, Hosokawa Toshinori (Nihon Univ.), Yoshimura Masayoshi (Kyoto Sangyo Univ.) VLD2017-31 DC2017-37 |
[more] | VLD2017-31 DC2017-37 pp.25-30 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 13:00 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | FPGA Implementation of Pattern Matching of PCRE for NIDS and its Acceleration and Memory Saving Masahiro Fukuda, Yasushi Inoguchi (JAIST) RECONF2017-37 |
In this paper, we explain about a development of a tool to automatically generate a circuit for pattern matching of Perl... [more] | RECONF2017-37 pp.1-6 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 13:25 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | RECONF2017-38 |
Graph processing has memory access with low locality, and it is not easy to process large-scale graphs which have the mi... [more] | RECONF2017-38 pp.7-12 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 13:50 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Ryo Kamasaka, Taisei Segawa, Yuichiro Shibata (Nagasaki Univ.) RECONF2017-39 |
(To be available after the conference date) [more] | RECONF2017-39 pp.13-18 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 14:30 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Reduction of Overhead in Adaptive Body Bias Technology due to Triple-well Structure Yasuhiro Ogasahara, Toshihiro Sekigawa, Hanpei Koike (AIST) VLD2017-32 DC2017-38 |
[more] | VLD2017-32 DC2017-38 pp.31-35 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 14:55 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Leakage Energy Reduction for Digital Embedded Memory using Dynamic Multi Body Bias Control Yusuke Yoshida, Kimiyoshi Usami (SIT) VLD2017-33 DC2017-39 |
Embedded memory macros are major central building blocks of any microprocessor and greatly affect power dissipation. In ... [more] | VLD2017-33 DC2017-39 pp.37-42 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 15:20 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | A shared memory chip for twin-tower of chips Sayaka Terashima, Takuya Kojima, Hayate Okuhara, Yusuke Matsushita, Naoki Ando (Keio Univ.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Hideharu Amano (Keio Univ.) VLD2017-34 DC2017-40 |
A shared memory chip for the building-block computing system using ThruChip Interface (TCI) is developed and evaluated.T... [more] | VLD2017-34 DC2017-40 pp.43-48 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 14:30 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | A Method of LFSR Seed Generation for Improving Quality of Delay Fault BIST Kyonosuke Watanabe, Satoshi Ohtake (Oita Univ.) VLD2017-35 DC2017-41 |
With the miniaturization and high speed of large scale integrated circuits, it has become important to test delay faults... [more] | VLD2017-35 DC2017-41 pp.49-54 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 14:55 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | An Approach to Selection of Classifiers and their Thresholds for Machine Learning Based Fail Chip Prediction Daichi Yuruki, Satoshi Ohtake (Oita Univ), Yoshiyuki Nakamura (Renesas Electronics) VLD2017-36 DC2017-42 |
Today, semiconductor technologies have developed and advance the integration density of LSI circuits. A technique which... [more] |
VLD2017-36 DC2017-42 pp.55-60 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 15:20 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | A Test Register Assignment Method to Reduce the Number of Test Patterns at Register Transfer Level Using Controller Augmentation Shun Takeda, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ) VLD2017-37 DC2017-43 |
Recently, it is very important to reduce the number of test patterns by using design-for-testability (DFT) with the incr... [more] | VLD2017-37 DC2017-43 pp.61-66 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 09:00 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Novel Implementation of FFT for Mixed Grained Reconfigurable Architecture Using Via-switch Tetsuaki Fujimoto (Ritsumeikan Univ.), Wataru Takahashi, Kazutoshi Wakabayashi (NEC), Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2017-38 DC2017-44 |
This report proposes an optimal implementation of FFT circuit for mixed grained reconfigurable architecture using via-sw... [more] | VLD2017-38 DC2017-44 pp.67-72 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 09:25 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Routing method considering programming constraint of reconfigurable device using via-switch crossbars Kosei Yamaguchi, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2017-39 DC2017-45 |
This report proposes a new routing method that considers constraint on the programming of switches in the reconfigurable... [more] | VLD2017-39 DC2017-45 pp.73-78 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 09:50 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | A PUF Based on the Instantaneous Response of Ring Oscillator Determined by the Convergence Time of Bistable Ring Oscillator Circuit Yuki Tanaka, Song Bian, Masayuki Hiromoto, Takashi Sato (Kyoto Univ.) VLD2017-40 DC2017-46 |
Studies on physical unclonable function (PUF) have been actively conducted as one of the countermeasures against counter... [more] | VLD2017-40 DC2017-46 pp.79-84 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 09:00 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Flip-Flop Selection for Multi-Cycle Test with Partial Observation in Scan-Based Logic BIST Shigeyuki Oshima, Takaaki Kato (Kyutech), Senling Wang (Ehime Univ.), Yasuo Sato, Seiji Kajihara (Kyutech) VLD2017-41 DC2017-47 |
A logic BIST scheme using multi-cycle test with partial observation has been proposed. In the scheme, the selection of f... [more] | VLD2017-41 DC2017-47 pp.85-90 |
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