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Technical Committee on Dependable Computing (DC) (Searched in: 2012)

Search Results: Keywords 'from:2013-02-13 to:2013-02-13'

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Search Results: Conference Papers

Conference Papers (Available on Advance Programs) (Sort by: Date Ascending)

Committee	Date Time	Place		Paper Title / Authors	Abstract	Paper #
DC	2013-02-13 10:00	Tokyo	Kikai-Shinko-Kaikan Bldg.	A Hardware Implementation of a SAT Solver for Test Generation with Solution Reuse Toshiya Mukai, Kenji Ueda, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2012-80	[more]	DC2012-80 pp.1-6
DC	2013-02-13 10:25	Tokyo	Kikai-Shinko-Kaikan Bldg.	Accelerating techniques for SAT-based test pattern generation Yusuke Matsunaga (Kyushu Univ.) DC2012-81	A naive way to solve ATPG problem using SAT solver is to formulate a test generation problem for a fault at a time. Thi... [more]	DC2012-81 pp.7-12
DC	2013-02-13 11:10	Tokyo	Kikai-Shinko-Kaikan Bldg.	Note on Fault Coverage Estimation Using Critical Area Analysis Yoshihiro Shimizu, Yuta Nakayama, Masayuki Arai, Kazuhiko Iwasaki (Tokyo Metro. Univ.) DC2012-82	[more]	DC2012-82 pp.13-18
DC	2013-02-13 11:35	Tokyo	Kikai-Shinko-Kaikan Bldg.	A don't care filling method to improve defect detection capability using stuck-at fault test sets and transition fault test sets Ryosuke Wakasugi, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyusyu Univ) DC2012-83	[more]	DC2012-83 pp.19-24
DC	2013-02-13 13:30	Tokyo	Kikai-Shinko-Kaikan Bldg.	Characteristic Analysis of Signal Delay for Resistive Open Fault Detection Hiroto Ohguri, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima), Toshiyuki Tsutsumi, Koji Yamazaki (Meiji Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) DC2012-84	When a resistive open fault occurs, signal delay at the faulty wire may degrade circuit performance. However, a resistiv... [more]	DC2012-84 pp.25-30
DC	2013-02-13 13:55	Tokyo	Kikai-Shinko-Kaikan Bldg.	On Fault detection method considering adjacent TSVs for a delay fault in TSV Masanori Nakamura, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ.of Tokushima) DC2012-85	We propose a fault detection method for a TSV (through-Silicon via) considering adjacent TSVs for detecting delay caused... [more]	DC2012-85 pp.31-36
DC	2013-02-13 14:40	Tokyo	Kikai-Shinko-Kaikan Bldg.	An evaluation of Trojan Circuits on AES Encryption Circuits Amy Ogita, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.) DC2012-86	[more]	DC2012-86 pp.37-42
DC	2013-02-13 15:05	Tokyo	Kikai-Shinko-Kaikan Bldg.	An Evaluatoin Method of Test Compactors for Secure Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.) DC2012-87	[more]	DC2012-87 pp.43-47
DC	2013-02-13 15:50	Tokyo	Kikai-Shinko-Kaikan Bldg.	A Method of Acceptable Fault Identification with Necessary Assignment in Logic Simplification for Error Tolerant Application Shingo Matsuki, Junpei Kamei, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2012-88	In error tolerant applications, some specific errors, which are of certain types or have severities within certain limit... [more]	DC2012-88 pp.49-54
DC	2013-02-13 16:15	Tokyo	Kikai-Shinko-Kaikan Bldg.	Temperature and voltage estimation considering manufacturing variability for a monitoring circuit Yousuke Miyake, Wataru Tsumori, Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.), Yukiya Miura (Tokyo Metropolitan Univ.) DC2012-89	Delay increase due to aging phenomena is a critical issue of VLSIs. For detecting such increase in field, a highly accur... [more]	DC2012-89 pp.55-60
DC	2013-02-13 16:40	Tokyo	Kikai-Shinko-Kaikan Bldg.	Data volume reduction method for unknown value handling in built-in self test used in field Yuta Yoshimi (NAIST), Kazumi Hatayama, Yuta Yamato, Tomokazu Yoneda, Michiko Inoue (NAIST/JST) DC2012-90	Many approaches on test pattern compression targeted unknown value handling. It is because unknown values have impacts o... [more]	DC2012-90 pp.61-66

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