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Technical Committee on Dependable Computing (DC) (Searched in: 2011)

Search Results: Keywords 'from:2012-02-13 to:2012-02-13'

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Search Results: Conference Papers

Conference Papers (Available on Advance Programs) (Sort by: Date Ascending)

Committee	Date Time	Place		Paper Title / Authors	Abstract	Paper #
DC	2012-02-13 10:00	Tokyo	Kikai-Shinko-Kaikan Bldg.	Design of Dual Edge Triggered Flip-Flops and Application to Signal Delay Detection Yoshihiro Ohkawa, Yukiya Miura (TMU) DC2011-76	Conventional edge triggered flip-flops sample a data signal synchronizing with single clock edge. If a noise signal occu... [more]	DC2011-76 pp.1-6
DC	2012-02-13 10:25	Tokyo	Kikai-Shinko-Kaikan Bldg.	An Evaluation of the Effects for Hardware Trojan Designs in AES Encryption Circuits Amy Ogita, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.) DC2011-77	[more]	DC2011-77 pp.7-12
DC	2012-02-13 11:05	Tokyo	Kikai-Shinko-Kaikan Bldg.	Pattern Merging for Additional Path Delay Fault Detection with Transition Delay Fault Test Hiroaki Tanaka, Kohei Miyase, Kazunari Enokimoto, Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2011-78	In this paper, we present to generate a test vector set to detect both transition and path delay faults. The proposed me... [more]	DC2011-78 pp.13-18
DC	2012-02-13 11:30	Tokyo	Kikai-Shinko-Kaikan Bldg.	Note on Layout-Aware High Accuracy Estimation of Fault Coverage Masayuki Arai, Yoshihiro Shimizu, Kazuhiko Iwasaki (Tokyo Metro. Univ.) DC2011-79	Shrinking feature size and higher integration on semiconductor device manufacturing technology bring a problem of the ga... [more]	DC2011-79 pp.19-24
DC	2012-02-13 11:55	Tokyo	Kikai-Shinko-Kaikan Bldg.	A method to reduce shift-toggle rate for low power BIST Takaaki Kato, Senling Wang, Kohei Miyase, Yasuo Sato, Seiji Kajihara (KIT) DC2011-80	Logic BIST using scan design has a problem with high power dissipation during test. In this work we propose a method tha... [more]	DC2011-80 pp.25-29
DC	2012-02-13 14:00	Tokyo	Kikai-Shinko-Kaikan Bldg.	A new problem at Boundary-Scan testing -- an internal disruption within IC during interconnect testing -- Shuichi Kameyama (Fujitsu & Ehime Univ.), Masayuki Baba (Fujitsu), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) DC2011-81	The miniaturization of electronic products is causing printed circuit boards to progress in the direction of higher dens... [more]	DC2011-81 pp.31-35
DC	2012-02-13 14:25	Tokyo	Kikai-Shinko-Kaikan Bldg.	A method to reduce the number of test patterns for transition faults using control point insertions Akihiko Takahashi, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ) DC2011-82	In recent year, the growing density and complexity for VLSIs cause an increase in the number of test patterns. Moreover,... [more]	DC2011-82 pp.37-42
DC	2012-02-13 14:50	Tokyo	Kikai-Shinko-Kaikan Bldg.	A Test Generation Method for Synchronously Designed QDI Circuits Koki Uchida, Eri Murata (NAIST), Satoshi Ohtake (Oita Univ.), Yasuhiko Nakashima (NAIST) DC2011-83	Quasi-Delay-Insensitive(QDI) design has been attracting attention as one of the practical techniques for implementation ... [more]	DC2011-83 pp.43-48
DC	2012-02-13 15:30	Tokyo	Kikai-Shinko-Kaikan Bldg.	An approach for adaptive determination of IDDQ testing criteria based on process parameter estimation Michihiro Shintani, Takashi Sato (Kyoto Univ.) DC2011-84	[more]	DC2011-84 pp.49-54
DC	2012-02-13 15:55	Tokyo	Kikai-Shinko-Kaikan Bldg.	Dynamic Test Scheduling for In-Field Aging Detection Yosuke Morinaga, Tomokazu Yoneda (NAIST), Hyunbean Yi (Hanbat National Univ.), Michiko Inoue (NAIST) DC2011-85	[more]	DC2011-85 pp.55-60
DC	2012-02-13 16:20	Tokyo	Kikai-Shinko-Kaikan Bldg.	Evaluation of a thermal and voltage estimation circuit for field test Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Kohei Miyase (Kyutech), Yukiya Miura (TMU) DC2011-86	High dependability is required for an embedded system VLSI. High functionality and high performance of VLSI, due to the ... [more]	DC2011-86 pp.61-66

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