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Technical Committee on Reconfigurable Systems (RECONF) (Searched in: 2017)
Search Results: Keywords 'from:2017-09-25 to:2017-09-25'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF | 2017-09-25 10:30 |
Tokyo | DWANGO Co., Ltd. | Pattern-matching-based game strategies and the strategy difference in pattern sizes Masataka Nakano, Yoshiki Yamaguchi (Univ. of Tsukuba)  RECONF2017-22 |
This paper proposes a template-based TRAX game player and unveils the significance of template sizes in the evaluation. ... [more] | RECONF2017-22 pp.1-6 |
| RECONF | 2017-09-25 10:55 |
Tokyo | DWANGO Co., Ltd. | A thorough investigation of FPGA performance for PCIe Gen3 communication Hiroki Nakamura, Hirotaka Takayama, Yoshiki Yamaguchi, Taisuke Boku (Univ. of Tsukuba) RECONF2017-23 |
(To be available after the conference date) [more] | RECONF2017-23 pp.7-12 |
| RECONF | 2017-09-25 13:30 |
Tokyo | DWANGO Co., Ltd. | RECONF2017-24 |
(To be available after the conference date) [more] | RECONF2017-24 pp.13-18 |
| RECONF | 2017-09-25 13:55 |
Tokyo | DWANGO Co., Ltd. | A Study of Applicability of FPGA Dynamic Partial Reconfiguration Technique on COTS-based Carrier Network Equipment with HW/SW Co-design Scheme Toru Homemoto, Hisaharu Ishii, Toshiya Matsuda, Masaru Katayama, Kazuyuki Matsumura (NTT) RECONF2017-25 |
The authors consider applying FPGA Dynamic Partial Reconfiguration (DPR) technique to carrier network equipment built wi... [more] | RECONF2017-25 pp.19-24 |
| RECONF | 2017-09-25 14:20 |
Tokyo | DWANGO Co., Ltd. | A Memory Reduction with Neuron Pruning for a Binarized Deep Convolutional Neural Network: Its FPGA Realization Tomoya Fujii, Shimpei Sato, Hiroki Nakahara (Tokyo Inst. of Tech.) RECONF2017-26 |
For a pre-trained deep convolutional neural network (CNN) for an embedded system, a high-speed and a low power consumpt... [more] |
RECONF2017-26 pp.25-30 |
| RECONF | 2017-09-25 15:00 |
Tokyo | DWANGO Co., Ltd. | Hardware acceleration for holographic memories on optically reconfigurable gate arrays Takumi Fujimori, Minoru Watanabe (Shizuoka Univ.) RECONF2017-27 |
[more] | RECONF2017-27 pp.31-36 |
| RECONF | 2017-09-25 15:25 |
Tokyo | DWANGO Co., Ltd. | Proplsal of reconfigurable system LSI with BiCS technology
-- Application to combination logic, FF, CMOS circuit and FPGA -- Shigeyoshi Watanabe (Shonan Inst. of Tech.), Tomohiro Yokota (DNP Data Techno), Shouto Tamai (Oi Electric), Takumi Sato (Japan Business Systems) RECONF2017-28 |
[more] | RECONF2017-28 pp.37-42 |
| RECONF | 2017-09-25 15:50 |
Tokyo | DWANGO Co., Ltd. | Performance analysis of Mono-Instruction Set Computer using VTR Hiroki Shinba, Minoru Watanabe (Shizuoka Univ.) RECONF2017-29 |
[more] | RECONF2017-29 pp.43-46 |
| RECONF | 2017-09-25 16:30 |
Tokyo | DWANGO Co., Ltd. | [Invited Talk]
Scalable and convertible FPGA DNN accelerator Shinichi Suto, Takato Yamada (LeapMind) RECONF2017-30 |
[more] | RECONF2017-30 pp.47-49 |
| RECONF | 2017-09-26 10:00 |
Tokyo | DWANGO Co., Ltd. | GUINNESS: A GUI based Binarized Deep Neural Network Framework for an FPGA Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Shimpei Sato (Tokyo Inst. of Tech.) RECONF2017-31 |
[more] | RECONF2017-31 pp.51-56 |
| RECONF | 2017-09-26 10:25 |
Tokyo | DWANGO Co., Ltd. | High-speed Calculation of k-means Clustering Using FPGA and its Application to Pick and Place Machine Shogo Nakamura, Hiroki Ebara, Kenji Kanazawa (Univ. of Tsukuba), Noriyuki Aibe (Keio Univ.), Moritoshi Yasunaga (Univ. of Tsukuba) RECONF2017-32 |
[more] | RECONF2017-32 pp.57-62 |
| RECONF | 2017-09-26 11:00 |
Tokyo | DWANGO Co., Ltd. | [Invited Talk]
Increasing Productivity Using Xilinx Development Tools Louie Valena (Xilinx) RECONF2017-33 |
Xilinx offers several tools to ease the development of complex hardware-software systems. Tools such as Vivado HLS, SDSo... [more] | RECONF2017-33 pp.63-68 |
| RECONF | 2017-09-26 13:30 |
Tokyo | DWANGO Co., Ltd. | RECONF2017-34 |
[more] | RECONF2017-34 pp.69-74 |
| RECONF | 2017-09-26 13:55 |
Tokyo | DWANGO Co., Ltd. | A case study of High-level Synthesis Using Higher-order Function on Functional Language Takuya Teraoka, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2017-35 |
The growing capabilities of silicon technology and the increasing complexity of applications in recent decades have forc... [more] | RECONF2017-35 pp.75-80 |
| RECONF | 2017-09-26 14:20 |
Tokyo | DWANGO Co., Ltd. | Implementing RISC-V with a Python-Based High-Level Synthesis Compiler Ryouzaburo Suzuki, Hiroaki Kataoka (Sinby) RECONF2017-36 |
During the last decade, the environment of field-programmable gate array (FPGA) development has changed rapidly, and the... [more] | RECONF2017-36 pp.81-86 |
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