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Special Interest Group on System Architecture (IPSJ-ARC)  (Searched in: 2019)

Search Results: Keywords 'from:2020-01-22 to:2020-01-22'
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Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Ascending)
 Results 1 - 20 of 40  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-22
11:00		 Kanagawa Raiosha, Hiyoshi Campus, Keio University
Honda Koki, Wei Kaijie (Keio Univ.), Arai Masatoshi (Saitama Univ.), Amano Hideharu (Keio Univ.) VLD2019-54 CPSY2019-52 RECONF2019-44		  [more] VLD2019-54 CPSY2019-52 RECONF2019-44
pp.1-5
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-22
11:25		 Kanagawa Raiosha, Hiyoshi Campus, Keio University Task offloading from vector processor to FPGA through PCIe connection
Kohei Hijikata (Tohoku Univ.), Tomohiro Ueno (RIKEN), Ryusuke Egawa, Hiroyuki Takizawa (Tohoku Univ.), Kentaro Sano (RIKEN) VLD2019-55 CPSY2019-53 RECONF2019-45		 (To be available after the conference date) [more] VLD2019-55 CPSY2019-53 RECONF2019-45
pp.7-11
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-22
11:50		 Kanagawa Raiosha, Hiyoshi Campus, Keio University DDR4 SDRAM controller for real-time processing
So Haramura, Nobuyuki Yamasaki (Keio Univ.) VLD2019-56 CPSY2019-54 RECONF2019-46		 Recently, larger scale programs are frequently used in embedded systems, and a higher capacity of main memory is require... [more] VLD2019-56 CPSY2019-54 RECONF2019-46
pp.13-17
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-22
13:30		 Kanagawa Raiosha, Hiyoshi Campus, Keio University A Consideration of NAT Traversal Function for MPI Runtime Environment on Android OS
Masahiro Nissato, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.) VLD2019-57 CPSY2019-55 RECONF2019-47		  [more] VLD2019-57 CPSY2019-55 RECONF2019-47
pp.19-24
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-22
13:55		 Kanagawa Raiosha, Hiyoshi Campus, Keio University VLD2019-58 CPSY2019-56 RECONF2019-48 (To be available after the conference date) [more] VLD2019-58 CPSY2019-56 RECONF2019-48
pp.25-30
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-22
14:20		 Kanagawa Raiosha, Hiyoshi Campus, Keio University Implementation and Evaluation of a Router on a Multi-FPGA System
Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Yugo Yamauchi, Kazuei Hironaka, Hideharu Amano (Keio Univ.) VLD2019-59 CPSY2019-57 RECONF2019-49		 The trade-off between power efficiency and performance is important in large-scale computing systems like a datacenter. ... [more] VLD2019-59 CPSY2019-57 RECONF2019-49
pp.31-36
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-22
14:45		 Kanagawa Raiosha, Hiyoshi Campus, Keio University Performance Evaluation of Using Multi-Switch on a Multi-FPGA System
Kohei Ito, Kensuke Iizuka, Yugo Yamauchi, Kazuei Hironaka (Keio Univ.), Yao Hu, Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) VLD2019-60 CPSY2019-58 RECONF2019-50		 Flow-in-Cloud(FiC) is a system which consists of multiple middle-range FPGAs connected by high-speed serial links, and i... [more] VLD2019-60 CPSY2019-58 RECONF2019-50
pp.37-42
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-22
15:25		 Kanagawa Raiosha, Hiyoshi Campus, Keio University Increasing Test Variation for C Compilers by Equivalent Mutant Generation
Hiroki Maeda, Nagisa ishiura (Kwansei Gakuin Univ.) VLD2019-61 CPSY2019-59 RECONF2019-51		 This article proposes a method of increasing variation of test programs in automatic testing of C compilers by means of ... [more] VLD2019-61 CPSY2019-59 RECONF2019-51
pp.43-48
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-22
15:50		 Kanagawa Raiosha, Hiyoshi Campus, Keio University Mutation Fuzzing Based on Type Estimation of Data Items Utilizing Data Writer
Yoko Higuchi, Nagisa Ishiura, Namba Noriyuki (Kwansei Gakuin Univ.) VLD2019-62 CPSY2019-60 RECONF2019-52		 This article proposes a novel way of acquiring information, which is used for enhancing efficiency of fuzzing for softwa... [more] VLD2019-62 CPSY2019-60 RECONF2019-52
pp.49-53
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-22
16:15		 Kanagawa Raiosha, Hiyoshi Campus, Keio University On logic locking method with affine transformation
Yusuke Matsunaga (Kyushu Univ.) VLD2019-63 CPSY2019-61 RECONF2019-53		  [more] VLD2019-63 CPSY2019-61 RECONF2019-53
pp.55-59
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-22
16:55		 Kanagawa Raiosha, Hiyoshi Campus, Keio University A Comparison of Filter for Convolutional Neural Network towards Hardware Implementation
Kosuke Akimoto, Youki Sada, Shimpei Sato, Hiroki Hakahara (Tokyo Tech) VLD2019-64 CPSY2019-62 RECONF2019-54		 Convolutional neural networks have high recognition accuracy in computer vision task, and many of the learned filters ar... [more] VLD2019-64 CPSY2019-62 RECONF2019-54
pp.61-66
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-22
17:20		 Kanagawa Raiosha, Hiyoshi Campus, Keio University Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks
Ryosuke Kuramochi, Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara (Titech) VLD2019-65 CPSY2019-63 RECONF2019-55		 A convolutional neural network (CNN) is one of the most successful neural networks and widely used for computer vision t... [more] VLD2019-65 CPSY2019-63 RECONF2019-55
pp.67-72
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-22
17:45		 Kanagawa Raiosha, Hiyoshi Campus, Keio University An FPGA Implementation of Monocular Depth Estimation
Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara (titech) VLD2019-66 CPSY2019-64 RECONF2019-56		 Among a lot of image recognition applications, Convolutional Neural Network (CNN) has gained high accuracy and increasin... [more] VLD2019-66 CPSY2019-64 RECONF2019-56
pp.73-78
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-23
09:30		 Kanagawa Raiosha, Hiyoshi Campus, Keio University An Efficient Cooperative Model Update using On-Device Learning
Rei Ito, Mineto Tsukada, Hiroki Matsutani (Keio Univ.) VLD2019-67 CPSY2019-65 RECONF2019-57		 (To be available after the conference date) [more] VLD2019-67 CPSY2019-65 RECONF2019-57
pp.79-84
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-23
09:55		 Kanagawa Raiosha, Hiyoshi Campus, Keio University A Light-Weight Reinforcement Learning using Online Sequential Learning
Hirohisa Watanabe, Mineto Tsukada, Hiroki Matsutani (Keio Univ.) VLD2019-68 CPSY2019-66 RECONF2019-58		 (To be available after the conference date) [more] VLD2019-68 CPSY2019-66 RECONF2019-58
pp.85-90
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-23
11:00		 Kanagawa Raiosha, Hiyoshi Campus, Keio University Memory access optimization for convolution with scheduling transformations of dependence graphs
Takayuki Todokoro, Kenshu Seto (TCU) VLD2019-69 CPSY2019-67 RECONF2019-59		  [more] VLD2019-69 CPSY2019-67 RECONF2019-59
pp.99-104
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-23
11:25		 Kanagawa Raiosha, Hiyoshi Campus, Keio University Full Hardware Synthesis of FreeRTOS-Based Systems
Wakako Nakano, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) VLD2019-70 CPSY2019-68 RECONF2019-60		  [more] VLD2019-70 CPSY2019-68 RECONF2019-60
pp.105-110
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-23
11:50		 Kanagawa Raiosha, Hiyoshi Campus, Keio University Binary Synthesis from RISC-V Executables
Shoki Hamana, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2019-71 CPSY2019-69 RECONF2019-61		 This article presents a method of synthesizing hardware from RISC-V binary codes. RISC-V is an open source instruction s... [more] VLD2019-71 CPSY2019-69 RECONF2019-61
pp.111-115
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-23
13:30		 Kanagawa Raiosha, Hiyoshi Campus, Keio University Design and implementation of a RISC-V computer system running Linux in Verilog HDL
Junya Miura, Hiromu Miyazaki, Kenji Kise (Tokyo Tech) VLD2019-72 CPSY2019-70 RECONF2019-62		 RISC-V is an instruction set architecture developed at the University of California, Berkeley.
Processors using RISC-V ... [more]		 VLD2019-72 CPSY2019-70 RECONF2019-62
pp.117-122
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-23
13:55		 Kanagawa Raiosha, Hiyoshi Campus, Keio University Design and implementation of a RISC-V soft processor adopting five-stage pipelining
Hiromu Miyazaki, Takuto Kanamori, Md Ashraful Islam, Kenji Kise (Tokyo Tech) VLD2019-73 CPSY2019-71 RECONF2019-63		 In this paper, we propose a RISC-V soft processor adopting five-stage pipelining optimized for FPGAs that support RV32I,... [more] VLD2019-73 CPSY2019-71 RECONF2019-63
pp.123-128
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