| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
Special Interest Group on System Architecture (IPSJ-ARC) (Searched in: 2007)
Search Results: Keywords 'from:2007-11-20 to:2007-11-20'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 10:05 |
Fukuoka | Kitakyushu International Conference Center | 2-Step Test Data Compression using Scan FF with Two Pattern Testability Kentaroh Katoh, Kazuteru Namba, Hideo Ito (Chiba Univ.)  VLD2007-70 DC2007-25 |
This paper presents a stuck-at test data compression technique using the scan flip flops with delay fault testability. T... [more] | VLD2007-70 DC2007-25 pp.1-6 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 10:30 |
Fukuoka | Kitakyushu International Conference Center | A Transition Delay Test Generation Method for Capture Power Reduction during At-Speed Scan Testing Tomoaki Fukuzawa, Kohei Miyase, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara (KIT) VLD2007-71 DC2007-26 |
High power dissipation can occur when a response to the test vector is captured by flip-flops in at-speed scan testing, ... [more] | VLD2007-71 DC2007-26 pp.7-12 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 10:55 |
Fukuoka | Kitakyushu International Conference Center | An optimization of thru trees for test generation based on acyclical testability Kohsuke Morinaga, Nobuya Oka, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2007-72 DC2007-27 |
The class of acyclic sequential circuits is $\tau^2$-bounded, i.e., acyclic sequential circuits are practically easily t... [more] | VLD2007-72 DC2007-27 pp.13-18 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 11:20 |
Fukuoka | Kitakyushu International Conference Center | An Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic Hiroaki Shimizu, Kiyoharu Hamaguchi, Toshinobu Kashiwabara (Osaka Univ.) |
Model checking technique, which is a method to verify systems automatically, have attracted attentions. Model checking, ... [more] | VLD2007-73 DC2007-28 pp.19-24 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 10:05 |
Fukuoka | Kitakyushu International Conference Center | A Memory Management Technique for Energy Reduction in Multi-Task Embedded Applications Seiichiro Yamaguchi, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) |
Memory systems consume a significant amount of the energy in embedded systems. Static code placement techniques using sc... [more] | VLD2007-74 DC2007-29 pp.25-29 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 10:30 |
Fukuoka | Kitakyushu International Conference Center | An ILP Model of Code Placement Problem for Minimizing the Energy Consumption in Embedded Processors Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) |
This paper formulates a code placement problem to optimize the total energy consumption of a CPU core, on-chip memories ... [more] | VLD2007-75 DC2007-30 pp.31-36 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 10:55 |
Fukuoka | Kitakyushu International Conference Center | A process-variation-aware low-power technique using current control Kyun-dong Kim, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya (Univ. of Tokyo) VLD2007-76 DC2007-31 |
Due to process variations, the difference of the operation speed between pipeline stages is increased,resulting in a num... [more] | VLD2007-76 DC2007-31 pp.37-42 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 11:20 |
Fukuoka | Kitakyushu International Conference Center | Proposal of domino-RSL circuit which is resistant to Differential Power Analysis attack on cryptographic circuit Yoshinobu Toyoda, Kenta Kido, Yoshiaki Shitabayashi, Takeshi Fujino (Ritsumeikan Univ.) VLD2007-77 DC2007-32 |
Countermeasures against Side Channel Attack are necessary to achieve cryptographic circuit that has tamper resistance. M... [more] | VLD2007-77 DC2007-32 pp.43-48 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 15:10 |
Fukuoka | Kitakyushu International Conference Center | A Method for Optimizing Communication Architecture on Network-on-Chip Considering Chip Size and Wiring Costs Daisuke Hayashi, Wataru Murai (Osaka Univ.), Akio Nakata (Hiroshima City Univ.), Tomoya Kitani, Keiichi Yasumoto (NAIST), Teruo Higashino (Osaka Univ.) CPSY2007-35 |
In this paper, we propose a method for deriving an optimal Network-on-Chip (NoC) communication architecture using intege... [more] | CPSY2007-35 pp.1-6 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 15:35 |
Fukuoka | Kitakyushu International Conference Center | Development of Inter-module Communication Mechanism for Dynamically Reconfigurable System Tomoyuki Ishida, Taiichiro Yatsunami, Osamu Kawaguchi, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) CPSY2007-36 |
In recent years, study of Programmable Logic Device, e.g. FPGAs, is much-investigated, and the dynamic reconfigurable sy... [more] | CPSY2007-36 pp.7-12 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 16:00 |
Fukuoka | Kitakyushu International Conference Center | KNIVES: Internet Based Distributed Shared Demand Side Management System Akihiro Oda, Tomokazu Tachikawa, Tomohiko Handa (Keio Univ.), Junichi Ichimura (Tokyo Gas Ltd.), Hiroaki Nishi (Keio Univ.) CPSY2007-37 |
KNIVES (Keio University Network oriented Intelligent and Versatile Energy saving System) is an IT based system,designed ... [more] | CPSY2007-37 pp.13-18 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 16:25 |
Fukuoka | Kitakyushu International Conference Center | FTN Simulation Technology Based on Analysis of Frequency, Time and Noise for High-speed Serial Communication System Goichi Ono, Takashi Takemoto, Koji Fukuda, Fumio Yuki, Ryo Nemoto, Eiichi Suzuki, Masayoshi Yagyu, Hiroki Yamashita, Tatsuya Saito (Hitachi) CPSY2007-38 |
We introduce a FTN simulation technology and its circuit behavior models for a high-speed serial communication system be... [more] | CPSY2007-38 pp.19-24 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 16:50 |
Fukuoka | Kitakyushu International Conference Center | The Evaluation of High-speed Serial Communication System by Using FTN Simulation Technology Takashi Takemoto, Goichi Ono, Koji Fukuda, Fumio Yuki, Ryo Nemoto, Eiichi Suzuki, Masayoshi Yagyu, Hiroki Yamashita, Tatsuya Saito (Hitachi) CPSY2007-39 |
We describe a FTN simulation technology for high-speed serial interface which is high-accuracy behavior model based on a... [more] | CPSY2007-39 pp.25-30 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 15:10 |
Fukuoka | Kitakyushu International Conference Center | A Development of the Auto mapping tool for embedded Programmable Logic matriX (ePLX) and the study of ePLX local architecture Kouta Ishibashi, Yoshiyuki Tanaka, Mitsutaka Matsumoto (Ritsumeikan Univ.), Hirofumi Nakano, Takenobu Iwao, Yoshihiro Okuno, Kazutami Arimoto (Renesas Technology), Masaya Yoshikawa (Meijo Univ.), Tomonori Izumi, Takeshi Fujino (Ritsumeikan Univ.) RECONF2007-32 |
We propose a ePLX(embedded Programmable Logic matriX)which will be embedded in SoC.The ePLX consists of small area and a... [more] | RECONF2007-32 pp.1-6 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 15:35 |
Fukuoka | Kitakyushu International Conference Center | A Study of Conection Block Structure and Implementation Methods of Multi-Input Functions for Variable Grain Logic Cell Kazunori Matsuyama, Ryoichi Yamaguchi, Yoshiaki Satou, Hiroshi Miura, Masahiro Koga, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2007-33 |
Since VGLC(Variable Grain Logic Cell) has a feature set both coarse-grained and fine-grained types, its structure can ... [more] |
RECONF2007-33 pp.7-12 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 16:00 |
Fukuoka | Kitakyushu International Conference Center | Track Swapping on Critical Paths Utilizing Random Variations for FPGAs to Enhance Speed and Yield Yuuri Sugihara, Youhei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ.) RECONF2007-34 |
FPGAs in future deep submicron fabrication process will suffer from drastic speed and yield loss caused by device variat... [more] | RECONF2007-34 pp.13-18 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 16:25 |
Fukuoka | Kitakyushu International Conference Center | Retrieving 3D infomation with streamed template matching Hidenori Matsubayashi, Shinsuke Nino, Toru Aramaki, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ) RECONF2007-35 |
Although real-time image processing is key to advanced robot vision systems, a conventional software approach with a ge... [more] |
RECONF2007-35 pp.19-24 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 15:10 |
Fukuoka | Kitakyushu International Conference Center | Comparison of Standard Cell Non-linear Asynchronous Pipelines Chammika Mannakkara, Tomohiro Yoneda (NII) VLD2007-78 DC2007-33 |
Two types of non-linear asynchronous pipeline constructs, namely Conditional Branch and Asynchronous were compared for 2... [more] | VLD2007-78 DC2007-33 pp.49-54 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 15:35 |
Fukuoka | Kitakyushu International Conference Center | An On-Chip Bus Architecture for Post-Fabrication Timing Calibration Masaki Yamaguchi, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) |
As the transistor size shrinks, the horizontal coupling capacitance between adjacent wires becomes dominant for wire loa... [more] | VLD2007-79 DC2007-34 pp.55-60 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 16:00 |
Fukuoka | Kitakyushu International Conference Center | Proposal and Circuit Performance Evaluation of Mask-less Via Programmable Device VPEX for EB Direct Writing Masahide Kawarasaki, Akihiro Nakamura, Tomoaki Nishimoto, Yoshiaki Shitabayashi, Takeshi Fujino (Ritsumeikan Univ.) VLD2007-80 DC2007-35 |
We propose the user-programmable device called VPEX (Via Programmable logic device using EXclusive-or array) which can c... [more] | VLD2007-80 DC2007-35 pp.61-66 |
[Return to Top Page]