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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF | 2016-09-05 16:35 |
Toyama | Univ. of Toyama | [Invited Talk]
Verification and Debugging Support Techniques for High-Level Designs Takeshi Matsumoto (INCT)  RECONF2016-31 |
[more] | RECONF2016-31 p.35 |
| IPSJ-SLDM, VLD | 2012-05-30 15:45 |
Fukuoka | Kitakyushu International Conference Center | High-level Design Debugging Using Potential Dependence Shohei Ono, Takeshi Matsumoto, Masahiro Fujita (Univ. of Tokyo) VLD2012-4 |
As high-level design draws more attention and has been adopted more widely, verification and debugging for high- level d... [more] | VLD2012-4 pp.19-24 |
| IPSJ-SLDM, VLD | 2012-05-31 11:20 |
Fukuoka | Kitakyushu International Conference Center | Statistical Analysis and its Hardware Implementation on Simulation Results of Systems with Uncertain Inputs Kosuke Oshima, Shohei Ono, Takeshi Matsumoto, Masahiro Fujita (Univ. of Tokyo) VLD2012-10 |
Statistical model checking is a method to analyze systems where variables have some uncertainty. It can be used to check... [more] | VLD2012-10 pp.55-60 |
| DC | 2010-06-25 16:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An I/O Sequence Slicing Method for Post-silicon Debugging Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita (Univ. of Tokyo.) DC2010-13 |
[more] | DC2010-13 pp.31-36 |
| DC | 2010-02-15 11:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Method of Reproducing Iuput/Ouput Error Trace on High-level Design for Hardware Debug Support Yeonbok Lee, Tasuku Nishihara, Takeshi Matsumoto (Univ. of Tokyo.), Masahiro Fujita (Univ. of Tokyo./JST) DC2009-69 |
[more] | DC2009-69 pp.25-30 |
| VLD | 2009-03-12 14:15 |
Okinawa | Automatic generation of Network-on-Chip topology under link length and latency constraint Hideo Tanida (Univ. of Tokyo), Hiroaki Yoshida (Univ. of Tokyo/JST-CREST), Takeshi Matsumoto (Univ. of Tokyo), Masahiro Fujita (Univ. of Tokyo/JST-CREST) VLD2008-148 |
With wire delay becoming dominant compared to transistor delay in deep-submicron era, the performance of SoC is more aff... [more] | VLD2008-148 pp.129-134 |
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| DC, CPSY, IPSJ-SLDM, IPSJ-EMB | 2009-03-05 17:00 |
Niigata | Sado Island Integrated Development Center | A post-silicon Debug Support Using Dynamic Program Slicing on High-level Design Description Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita (Univ. of Tokyo) CPSY2008-93 DC2008-84 |
[more] | CPSY2008-93 DC2008-84 pp.31-36 |
| DC, CPSY, IPSJ-SLDM, IPSJ-EMB | 2009-03-05 17:30 |
Niigata | Sado Island Integrated Development Center | Debugging Support for Synchronization of Parallel Execution in System Level Designs Hiroki Harada, Tasuku Nishihara, Takeshi Matsumoto (Tokyo University), Masahiro Fujita (Tokyo University/JST) CPSY2008-94 DC2008-85 |
There are many high-level designs contain parallel execution, synchronization, or communication, and they are often erro... [more] | CPSY2008-94 DC2008-85 pp.37-42 |
| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-30 08:40 |
Kanagawa | Automatic Equivalence Specification between Two Sequential Circuits in High-level Design Jinmei Xu, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita (University of Tokyo) VLD2008-109 CPSY2008-71 RECONF2008-73 |
[more] | VLD2008-109 CPSY2008-71 RECONF2008-73 pp.105-110 |
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| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-30 09:05 |
Kanagawa | Formal Verification Method for Protocol Transducer Using Automatically Generated Properties from Specification Fei Gao, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita (Univ. of Tokyo) VLD2008-110 CPSY2008-72 RECONF2008-74 |
IP-reuse design is widely applied in order to reduce design period by utilizing already designed and well verified modul... [more] | VLD2008-110 CPSY2008-72 RECONF2008-74 pp.111-116 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 13:25 |
Fukuoka | Kitakyushu Science and Research Park | Generation of High Coverage Property Set Using Counterexamples Takeshi Matsumoto, Yeonbok Lee, Hiroaki Yoshida (Univ. of Tokyo), Hisashi Yomiya (Toshiba Corporation), Masahiro Fujita (Univ. of Tokyo) |
[more] | VLD2008-79 DC2008-47 pp.115-120 |
| DC, CPSY, IPSJ-SLDM, IPSJ-EMB | 2008-03-28 10:30 |
Kagoshima | A technique of automatic input pattern generation for system-level design descriptions by concrete and symbolic simulations Yoshihisa Kojima, Tasuku Nishihara, Takeshi Matsumoto (Univ. of Tokyo), Masahiro Fujita (VDEC, Univ of Tokyo) DC2007-106 CPSY2007-102 |
As the VLSI systems grow larger and more complicated, it becomes more difficult to manually prepare the input patterns o... [more] | DC2007-106 CPSY2007-102 pp.133-138 |
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| VLD, ICD | 2008-03-06 15:05 |
Okinawa | TiRuRu | Performance Estimation considering False-paths for System-level Design Daisuke Ando, Takeshi Matsumoto, Tasuku Nishihara, Masahiro Fujita (Univ. of Tokyo) VLD2007-152 ICD2007-175 |
In designing today's highly complicated system-LSIs, it is essential to estimate timing information such as worst-case o... [more] | VLD2007-152 ICD2007-175 pp.49-54 |
| ICD, VLD | 2007-03-07 15:20 |
Okinawa | Mielparque Okinawa | Design Checker for System-Level Design using Extended System Dependence Graph Daisuke Ando, Takeshi Matsumoto, Tasuku Nishihara, Masahiro Fujita (Univ. of Tokyo) |
In designing system LSI or System-on-a-Chip (SoC), it is essential to find and correct design errors as early design sta... [more] | VLD2006-112 ICD2006-203 pp.37-42 |
| VLD, IPSJ-SLDM | 2006-05-12 09:30 |
Ehime | Ehime University | An Approach to Formal Equivalence Checking by Symbolic Simulation between Behavioral and RTL Designs Takeshi Matsumoto, Satoshi Komatsu, Masahiro Fujita (Univ. of Tokyo) |
[more] | VLD2006-7 pp.7-12 |
| ICD, VLD | 2006-03-09 09:15 |
Okinawa | Verifying Deep Bugs by Model Checking and Inductive Approach Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita (Tokyo Univ.) |
[more] | VLD2005-108 ICD2005-225 pp.1-6 |
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