| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-19 16:15 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Reinforcing Generation of Control Flow Statements in Random Test System of C Compilers Based on Equivalence Transformation Mitsuyoshi Iwatsuji, Nagisa Ishiura (Kwansei Gakuin Univ.)  VLD2017-87 CPSY2017-131 RECONF2017-75 |
This article proposes a method of reinforcing generation of control statements in random testing of compilers based on e... [more] | VLD2017-87 CPSY2017-131 RECONF2017-75 pp.163-168 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-19 16:40 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Mutant Generation of Performance Tests for LLVM Back-Ends Kenji Tanaka, Nagisa Ishiura (Kwansei Gakuin Univ.), Masanari Nishimura, Akiya Fukui (Renesas) VLD2017-88 CPSY2017-132 RECONF2017-76 |
This article presents a method of testing optimization capability of LLVM back-ends by generating functionally equivalen... [more] | VLD2017-88 CPSY2017-132 RECONF2017-76 pp.169-174 |
| VLD | 2016-02-29 13:55 |
Okinawa | Okinawa Seinen Kaikan | Random Testing of C Compilers Based on Test Program Generation by Equivalence Transformation Kazuhiro Nakamura, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2015-112 |
This article proposes a method of generating test programs for random testing of C compilers based on equivalence transf... [more] | VLD2015-112 pp.7-12 |
| VLD | 2016-02-29 15:00 |
Okinawa | Okinawa Seinen Kaikan | High-Level Synthesis of Embedded Systems Controller from Erlang Hinata Takabeyashi, Nagisa Ishiura, Kagumi Azuma (Kwansei Gakuin Univ), Nobuaki Yoshida, Hiroyuki Kanbara (ASTEM) VLD2015-114 |
This article presents a method of specifying the behavior of embedded systems' control by a subset of Erlang and synthes... [more] | VLD2015-114 pp.19-24 |
| VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] | 2016-01-21 13:00 |
Kanagawa | Hiyoshi Campus, Keio University | Mainframe Assembly to C translation in Legacy Migration Daisuke Fujiwara, Nagisa Ishiura, Ryo Sakai (Kwansei Gakuin Univ.), Ryo Aoki, Takashi Ogawara (SYSTEM'S) VLD2015-104 CPSY2015-136 RECONF2015-86 |
This article presents a method of translating mainframe assembly programs to C programs. In ``legacy migration,'' where ... [more] | VLD2015-104 CPSY2015-136 RECONF2015-86 pp.203-208 |
| VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] | 2016-01-21 13:50 |
Kanagawa | Hiyoshi Campus, Keio University | Binary Synthesis Implementing External Interrupt Handler as Independent Module Naoya Ito, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) VLD2015-106 CPSY2015-138 RECONF2015-88 |
[more] | VLD2015-106 CPSY2015-138 RECONF2015-88 pp.215-220 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 09:45 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Extending Distributed Control for High-Level Synthesis beyond Boundaries of Dataflow Graphs Miho Shimizu, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2015-61 DC2015-57 |
This paper proposes an extension of distributed control, which enables efficient run-time scheduling of variable latency... [more] | VLD2015-61 DC2015-57 pp.153-158 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 14:10 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Exploration of Address Offsets of Basic Blocks for Cache Hit Ratio Improvement Junya Goto, Nagisa Ishiura (K.G.) VLD2015-74 DC2015-70 |
This article proposes a method of reducing cache misses on an instruction memory by inserting offsets before basic block... [more] | VLD2015-74 DC2015-70 pp.237-241 |
| RECONF, CPSY, VLD, IPSJ-SLDM [detail] | 2015-01-29 18:00 |
Kanagawa | Hiyoshi Campus, Keio University | CF3: Test suite for arithmetic optimization of C compilers Yusuke Hibino, Nagisa Ishiura (KGU) VLD2014-130 CPSY2014-139 RECONF2014-63 |
This article presents a compiler test suite "CF3," which targets arithmetic optimization, especially constant folding, o... [more] | VLD2014-130 CPSY2014-139 RECONF2014-63 pp.117-122 |
| RECONF, CPSY, VLD, IPSJ-SLDM [detail] | 2015-01-30 11:30 |
Kanagawa | Hiyoshi Campus, Keio University | Detecting Missed Arithmetic Optimization Opportunities Using Random Testing of C Compilers Atsushi Hashimoto, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2014-139 CPSY2014-148 RECONF2014-72 |
This article presents new methods of detecting missed arithmetic optimization opportunities of C compilers by random tes... [more] | VLD2014-139 CPSY2014-148 RECONF2014-72 pp.169-174 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-29 14:10 |
Kanagawa | Hiyoshi Campus, Keio University | Dynamic Operation Binding in Distributed Controller for Supporting Functional Units with Variable Latency Shinji Yamashita, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2013-128 CPSY2013-99 RECONF2013-82 |
This article presents a new distributed method for controlling circuits with variable latency units, which can dynamical... [more] | VLD2013-128 CPSY2013-99 RECONF2013-82 pp.155-160 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-29 16:20 |
Kanagawa | Hiyoshi Campus, Keio University | PerCUDA: CUDA Binding Framework for Perl Takayuki Fukumoto, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2013-132 CPSY2013-103 RECONF2013-86 |
This article presents ``PerCUDA,'' which is a framework of GPGPU by way of script language Perl. In PerCUDA, kernel fun... [more] |
VLD2013-132 CPSY2013-103 RECONF2013-86 pp.179-184 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-29 16:45 |
Kanagawa | Hiyoshi Campus, Keio University | Binary Synthesis of Hardware Accelerator Tightly Coupled with CPU Shimpei Tamura, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Kanbara (ASTEM), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2013-133 CPSY2013-104 RECONF2013-87 |
This article presents a method of synthesizing hardware that accelerates specified sections of binary programs. The acce... [more] | VLD2013-133 CPSY2013-104 RECONF2013-87 pp.185-190 |
| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-16 15:35 |
Kanagawa | Scaling the size of Expressions in Random Testing of Arithmetic Optimization of C Compilers Eriko Nagai, Atsushi Hashimoto, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2012-117 CPSY2012-66 RECONF2012-71 |
This paper presents an enhanced method of testing validity of arithmetic optimization of C compilers using random progra... [more] | VLD2012-117 CPSY2012-66 RECONF2012-71 pp.57-62 |
|
| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-16 16:25 |
Kanagawa | Speeding up multiple sections of binary code by hardware accelerator tightly coupled with cpu Shunsuke Satake (Kwansei Gakuin Univ), Nagisa Ishiura, Shimpei Tamura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ), Hiroyuki Kanbara (ASTEM) VLD2012-119 CPSY2012-68 RECONF2012-73 |
This article presents an improvement over the hardware accelerator tightly coupled with a CPU. While the previously pr... [more] |
VLD2012-119 CPSY2012-68 RECONF2012-73 pp.69-73 |
|
| VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2012-01-26 09:00 |
Kanagawa | Hiyoshi Campus, Keio University | Merge of Functions in High-Level Synthesis using Assembly Codes as Intermediate Representation Fumiaki Takashima, Nagisa Ishiura, Makoto Orino (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) VLD2011-106 CPSY2011-69 RECONF2011-65 |
This article presents a method of merging functions during high-level synthesis whose inputs are assembly codes generate... [more] | VLD2011-106 CPSY2011-69 RECONF2011-65 pp.89-94 |
| VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2012-01-26 09:25 |
Kanagawa | Hiyoshi Campus, Keio University | High-Level Synthesis of Hardware Relinkable to Software Makoto Orino, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Fumiaki Takashima (Kwansei Gakuin Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) VLD2011-107 CPSY2011-70 RECONF2011-66 |
This article presents a method of synthesizing {\em relinkable} hardware for hardware/software codesign utilizing high-l... [more] | VLD2011-107 CPSY2011-70 RECONF2011-66 pp.95-100 |
| MSS, CAS, VLD, SIP | 2011-07-01 10:50 |
Okinawa | Okinawa-Ken-Seinen-Kaikan | [Panel Discussion]
Toward new developments of System and Signal Processing Subsociety Nagisa Ishiura (Kwansei Gakuin Univ.), Mitsunori Makino (Chuo Univ.), Kimiyoshi Usami (Shibaura Institute of Technology), Isao Yamada (Tokyo Institute of Technology), Kunihiko Hiraishi (JAIST), Shingo Yamaguchi (Yamaguchi Univ.), Masaki Nakamura (Toyama Pref. Univ.) CAS2011-22 VLD2011-29 SIP2011-51 MSS2011-22 |
[more] | CAS2011-22 VLD2011-29 SIP2011-51 MSS2011-22 p.127 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] | 2011-03-19 14:45 |
Okinawa | Parallel C code generation from Simulink models Takahiro Kumura (NEC/Osaka Univ.), Masato Edahiro, Yuichi Nakamura (NEC), Nagisa Ishiura (Kwansei Gakuin Univ.), Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) CPSY2010-80 DC2010-79 |
This paper proposes a method to generate parallel C code from models developed on the Simulink which is a model-based ... [more] |
CPSY2010-80 DC2010-79 pp.303-308 |
|
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-17 13:30 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Approximated Variable Scheduling for High-Level Synthesis Kousuke Sone, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2010-90 CPSY2010-45 RECONF2010-59 |
This article presents approximated variable scheduling methods for high-level synthesis. In the presence of indefinite c... [more] | VLD2010-90 CPSY2010-45 RECONF2010-59 pp.37-42 |
[Return to Top Page]