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Committee Date Time Place Paper Title / Authors Abstract Paper #
HWS, VLD 2019-02-27
13:05		 Okinawa Okinawa Ken Seinen Kaikan Wire Load Model for Power Consumption Evaluation of Via-Switch FPGA
Asuka Natsuhara, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2018-97 HWS2018-60		 In this report, we consider a wire load model for an FPGA using new nano-device called via-switch to allow power estimat... [more] VLD2018-97 HWS2018-60
pp.25-30
IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2018-01-19
11:05		 Kanagawa Raiosha, Hiyoshi Campus, Keio University A study on the power efficiency of via-switch oriented programmable logic 0-1-A-~A LUT
Asuka Natsuhara, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2017-80 CPSY2017-124 RECONF2017-68		 This paper quantitatively shows the superiority of 0-1-$A$-$overline{A}$ LUT to 0-1 LUT in terms of area, delay time and... [more] VLD2017-80 CPSY2017-124 RECONF2017-68
pp.107-112
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]		 2016-11-29
10:30		 Osaka Ritsumeikan University, Osaka Ibaraki Campus Area-efficient LUT-like Programmable Logic Using Atom Switch and its Delay-optimal Mapping Algorithm
Toshiki Higashi, Hiroyuki Ochi (Ritsumeikan Univ.) RECONF2016-45		 This paper proposes a delay model for 0-1-$A$-$overline{A}$ LUT and a delay-optimal mapping algorithm for it. 0-1-$A$-$o... [more] RECONF2016-45
pp.29-34
ICD 2013-04-12
08:30		 Ibaraki Advanced Industrial Science and Technology (AIST) [Invited Talk] Complementary atom-switch based programmable cell array and its demostraion of logic mapping synthesized from RTL code
Makoto Miyamura, Munehiro Tada, Toshitsugu Sakamoto, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiromitsu Hada (LEAP) ICD2013-12		 Reconfigurable nonvolatile programmable-logic using complementary atom switch (CAS) is successfully demonstrated on a 65... [more] ICD2013-12
pp.55-59
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