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Committee
Date Time
Place
Paper Title / Authors
Abstract
Paper #
ICD
2006-04-13
10:45
Oita
Oita University
[Special Invited Talk] Sub-1V DRAM Design
Takayuki Kawahara
(
Hitachi Central Research Lab.
)
Issues for sub-1V DRAM operation and its solutions are described. Since the low voltage operation of DRAM is difficult,...
[more]
ICD2006-4
pp.19-24
EE
2005-11-11
17:15
Tokyo
Kikai-Shinko-Kaikan Bldg.
Power factor-corrective circuit without sine-wave reference
Koichi Morita
(
Office Morita
)
As the limits for harmonic current emission was enshrined into law and many countries started to adopt it. So with the p...
[more]
EE2005-46
pp.43-46
ICD
2005-04-15
10:30
Fukuoka
A 1.2V 1Mbit Embedded MRAM Core with Folded Bit-Line Array Architecture
Takaharu Tsuji
(
Renesas Technorogy
),
Hiroaki Tanizaki
(
Renesas Device Design
),
Masatoshi Ishikawa
,
Jun Otani
,
Yuichiro Yamaguchi
,
Shuichi Ueno
,
Tsukasa Oishi
,
Hideto Hidaka
(
Renesas Technorogy
)
A 1Mbit MRAM with a 0.81um2 1-Transistor 1-Magnetic Tunnel Junction (1T-1MTJ) cell using 0.13um 4LM logic technology has...
[more]
ICD2005-13
pp.1-6
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