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Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) (Searched in: 2006)
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Search Results: Keywords 'from:2006-05-11 to:2006-05-11'
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| [Go to Official IPSJ-SLDM Homepage (Japanese)] |
| Search Results: Conference Papers |
| Conference Papers (Available on Advance Programs) (Sort by: Date Ascending) |
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| Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
| VLD, IPSJ-SLDM |
2006-05-11
14:00 |
Ehime |
Ehime University |
Online FPGA Placement Using I/O Routing Information
Mitsuru Tomono, Masaki Nakanishi, Shigeru Yamashita (NAIST), Kazuo Nakajima (Univ. of Maryland), Katsumasa Watanabe (NAIST) |
[more] |
VLD2006-1
pp.1-6 |
| VLD, IPSJ-SLDM |
2006-05-11
14:30 |
Ehime |
Ehime University |
Dynamic Reconfigurable Wiring Architecture and Its Application to Hardware Mapping
Shinji Kimura (Waseda Univ.) |
Reconfigurable architecture is one of key technologies to cope with bugs and the specification changes of systerm LSI. E... [more] |
VLD2006-2
pp.7-12 |
| VLD, IPSJ-SLDM |
2006-05-11
15:00 |
Ehime |
Ehime University |
A Software-level Energy Reduction Technique for Embedded Microprocessor Exploiting Narrow Bitwidth Operations
Seiichiro Yamaguchi, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) |
This paper proposes a software-level energy reduction technique for microprocessor-based embedded systems. A basic idea ... [more] |
VLD2006-3
pp.13-18 |
| VLD, IPSJ-SLDM |
2006-05-11
15:30 |
Ehime |
Ehime University |
Automatic Generation of Custom Instructions with Memory Access and Resource Sharing
Kenshu Seto, Masahiro Fujita (Univ. of Tokyo) |
[more] |
VLD2006-4
pp.19-24 |
| VLD, IPSJ-SLDM |
2006-05-11
16:15 |
Ehime |
Ehime University |
[Invited Talk]
Configurable Processor Design Environment ASIP Meister
Masaharu Imai, Ittetsu Taniguchi, Yoshinori Takeuchi, Keishi Sakanushi (Osaka Univ.) |
[more] |
VLD2006-5
pp.25-30 |
| VLD, IPSJ-SLDM |
2006-05-12
09:00 |
Ehime |
Ehime University |
Bottom-up Equivalence Checking for SpecC Programs
Subash Shankar (City Univ. of New York), Masahiro Fujita (Univ. of Tokyo) |
[more] |
VLD2006-6
pp.1-6 |
| VLD, IPSJ-SLDM |
2006-05-12
09:30 |
Ehime |
Ehime University |
An Approach to Formal Equivalence Checking by Symbolic Simulation between Behavioral and RTL Designs
Takeshi Matsumoto, Satoshi Komatsu, Masahiro Fujita (Univ. of Tokyo) |
[more] |
VLD2006-7
pp.7-12 |
| VLD, IPSJ-SLDM |
2006-05-12
10:00 |
Ehime |
Ehime University |
An Implementation of a Ternary-valued Logic Simulator using a Value-independent Simulator Kernel
Takatomi Wada, Yasushi Hibino (JAIST) |
In multi-valued logic, the expression by a little number of digits can be possible. So the integration of LSI is improve... [more] |
VLD2006-8
pp.13-18 |
| VLD, IPSJ-SLDM |
2006-05-12
10:45 |
Ehime |
Ehime University |
Efficient generation method of indirect implication on ATPG
Masayoshi Yoshimura (FLEETS), Seiji Kajihara (KIT), Yusuke Matsunaga (Kyushu University) |
[more] |
VLD2006-9
pp.19-23 |
| VLD, IPSJ-SLDM |
2006-05-12
11:15 |
Ehime |
Ehime University |
Power-Conscious Microprocessor-Based Testing of System-on-Chip
Fawnizu Azmadi Hussin, Tomokazu Yoneda (NAIST), Alex Orailoglu (Univ. of California), Hideo Fujiwara (NAIST) |
In this paper, we are proposing a core-based test methodology that utilizes the functional bus for test stimuli and resp... [more] |
VLD2006-10
pp.25-30 |
| VLD, IPSJ-SLDM |
2006-05-12
13:00 |
Ehime |
Ehime University |
Reduction of Equalizing Circuit Area for 8-VSB Demodulator Using the Result of Correlation Operation
Kazumi Kawashima, Yusuke Konishi, Yusuke Hashiguchi, Yuu Yamamoto, Masahiro Numa (Kobe Univ.) |
[more] |
VLD2006-11
pp.31-36 |
| VLD, IPSJ-SLDM |
2006-05-12
13:30 |
Ehime |
Ehime University |
Delay and Power Consumption of Integer Multipiler
-- Comparison of Wallace and Dadda tree --
Masayoshi Tachibana (KUT) |
[more] |
VLD2006-12
pp.37-40 |
| VLD, IPSJ-SLDM |
2006-05-12
14:00 |
Ehime |
Ehime University |
Measurement and Analysis of Delay and Power Variations in 90nm CMOS Circuits
Masaki Yamaguchi (Kyushu Univ.), Yang Yuan (Xi'an Univ. of Technology), Kosuke Tarumi, Ryota Sakamoto, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) |
As the transistor size shrinks, process variations increase. Under the existence of the variations, an existing design f... [more] |
VLD2006-13
pp.41-46 |
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