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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SDM, ICD, ITE-IST [detail] | 2021-08-18 13:45 |
Online | Online | Performance Evaluation of Serial-Parallel Montgomery Multipliers for RNS Hiroyuki Tsubouchi, Mitsunaga Kinjo, Katsuhiko Shimabukuro (Univ. of the Ryukyus)  SDM2021-40 ICD2021-11 |
Modulo operations are required in RNS (Residue Number System) which enables to perform highly parallel computation. Also... [more] | SDM2021-40 ICD2021-11 pp.54-57 |
| HWS, ICD | 2018-10-29 14:55 |
Osaka | Kobe Univ. Umeda Intelligent Laboratory | Selection and evaluation of optimal bases in the case of implementing Q-RNS MR algorithm in FPGA Yoshihiro Kori, Daisuke Fujimoto, Yu-ichi Hayasi (NAIST), Naofumi Homma (Tohoku Univ.) HWS2018-51 ICD2018-43 |
To improve a computation speed of public cryptography, Montgomery Reduction(MR) and Residue Number System (RNS) are ofte... [more] | HWS2018-51 ICD2018-43 pp.25-30 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-01 13:10 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Implementation of ECDSA Using Gate-level Pipelined Self-synchronous Circuit Masato Tamura, Makoto Ikeda (Univ. of Tokyo) VLD2015-39 DC2015-35 |
In this paper, we investigated the implementation method of elliptic curve digital signature algorithm using self-synchr... [more] | VLD2015-39 DC2015-35 pp.7-12 |
| CPSY | 2014-11-14 10:15 |
Hiroshima | Hiroshima University | C2CU : A CUDA C Program Generator for Bulk Execution of a Sequential Algorithm Daisuke Takafuji, Koji Nakano, Yasuaki Ito (Hiroshima Univ.) CPSY2014-67 |
A sequential algorithm is oblivious if an address accessed at each time does not depend on input data. Many important ta... [more] | CPSY2014-67 pp.75-80 |
| ISEC | 2011-05-13 16:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Study on Side Channel Cryptanalysis of RSA Hardware Focused on Operands for Multiple-precision Multiplication Takeshi Kishikawa, Tsutomu Matsumoto (YNU) ISEC2011-8 |
A lot of side channel attack methods and countermeasures have been studied for modular powering based cryptosystems such... [more] | ISEC2011-8 pp.51-57 |
| IT, ISEC, WBS | 2010-03-04 17:25 |
Nagano | Nagano-Engineering Campus, Shinshu University | An RSA Encryption Hardware Algorithm that uses a DSP block on the FPGA Kensuke Kawakami, Koji Nakano (Hiroshima Univ.) IT2009-80 ISEC2009-88 WBS2009-59 |
The main contribution of this paper is to present an efficient hardware algorithm for modular exponentiation, which is a... [more] | IT2009-80 ISEC2009-88 WBS2009-59 pp.61-68 |
| CAS, SIP, VLD | 2007-06-22 13:00 |
Hokkaido | Hokkaido Tokai Univ. （Sapporo) | Scalable Dual-Radix Unified Montgomery Multiplier in GF(p) and GF(2n) Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) CAS2007-26 VLD2007-42 SIP2007-56 |
Modular multiplication is the dominant arithmetic operation in elliptic curve cryptography (ECC), which is one of public... [more] | CAS2007-26 VLD2007-42 SIP2007-56 pp.43-48 |
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