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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2014-11-28
15:35		 Oita B-ConPlaza [Invited Talk] An approach for 30Gb/s optical LSI volume testing
Daisuke Watanabe (Advantest), Shin Masuda (ADVANTEST Lab) CPM2014-129 ICD2014-72		 With increasing data transmission capacity due to cloud computing, datacenters have an increased need for lower power an... [more] CPM2014-129 ICD2014-72
pp.39-42
IPSJ-SLDM, CPSY, RECONF, VLD [detail] 2014-01-28
10:25		 Kanagawa Hiyoshi Campus, Keio University A Storing and Regenerating Signal Information in a Scalable Hardware System
Yusuke Katoh, Daisuke Watanabe, Hironori Nakajo (Tokyo Univ. of Agriculture and Tech) VLD2013-106 CPSY2013-77 RECONF2013-60		 In implementing a large-scale circuit into a single LSI, limitation of circuit area or degradation of maximum operating ... [more] VLD2013-106 CPSY2013-77 RECONF2013-60
pp.25-30
IPSJ-SLDM, CPSY, RECONF, VLD [detail] 2014-01-28
10:50		 Kanagawa Hiyoshi Campus, Keio University Hardware Expansion Protocol in a Scalable Hardware System
Daisuke Watanabe, Yusuke Katoh, Hironori Nakajo (Tokyo Univ. of Agriculture and Tech.) VLD2013-107 CPSY2013-78 RECONF2013-61		 Recently hardware acceleration with using an FPGA are focused as well as prototyping an ASIC with it. The available numb... [more] VLD2013-107 CPSY2013-78 RECONF2013-61
pp.31-36
ICD 2006-05-26
14:45		 Hyogo Kobe University 1.83ps-Resolution CMOS Dynamic Arbitrary Timing Generator for >4GHz ATE Applications
Toshiyuki Okayasu, Masakatsu Suda, Kazuhiro Yamamoto, Shusuke Kantake, Satoshi Sudou, Daisuke Watanabe (Advantest) 		A high-speed, precise fully CMOS dynamic arbitrary timing generator for >4GHz automatic test equipment (ATE) application... [more] ICD2006-36
pp.83-87
ICD 2005-05-27
16:10		 Hyogo Kobe Univ. A Programmable On-Chip Picosecond Jitter Measurement Circuit without a Reference Clock
Kiyotaka Ichiyama, Masahiro Ishida, Takahiro Yamaguchi (Advantest Labs.), Mani Soma (Univ. of Washington), Masakatsu Suda, Toshiyuki Okayasu, Daisuke Watanabe, Kazuhiro Yamamoto (Advantest) 		A new on-chip jitter measurement circuit, which does not require a reference clock, is proposed. It consists of a combin... [more] ICD2005-38
pp.57-60
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